| T1083 |
/workspace/coverage/default/1.flash_ctrl_sec_info_access.2718527852 |
|
|
Jul 15 07:31:14 PM PDT 24 |
Jul 15 07:32:28 PM PDT 24 |
569769200 ps |
| T1084 |
/workspace/coverage/default/47.flash_ctrl_connect.181039375 |
|
|
Jul 15 07:36:45 PM PDT 24 |
Jul 15 07:36:59 PM PDT 24 |
19145400 ps |
| T1085 |
/workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.791710429 |
|
|
Jul 15 07:35:34 PM PDT 24 |
Jul 15 07:36:06 PM PDT 24 |
48481900 ps |
| T1086 |
/workspace/coverage/default/16.flash_ctrl_rw_evict.1945435880 |
|
|
Jul 15 07:34:05 PM PDT 24 |
Jul 15 07:34:38 PM PDT 24 |
117453700 ps |
| T1087 |
/workspace/coverage/default/37.flash_ctrl_alert_test.3123796984 |
|
|
Jul 15 07:36:11 PM PDT 24 |
Jul 15 07:36:26 PM PDT 24 |
38391100 ps |
| T1088 |
/workspace/coverage/default/13.flash_ctrl_intr_rd.1926997436 |
|
|
Jul 15 07:33:32 PM PDT 24 |
Jul 15 07:37:12 PM PDT 24 |
6625428900 ps |
| T1089 |
/workspace/coverage/default/3.flash_ctrl_ro_derr.2258598856 |
|
|
Jul 15 07:31:34 PM PDT 24 |
Jul 15 07:34:47 PM PDT 24 |
1181435600 ps |
| T1090 |
/workspace/coverage/default/47.flash_ctrl_otp_reset.1474062831 |
|
|
Jul 15 07:36:44 PM PDT 24 |
Jul 15 07:38:55 PM PDT 24 |
114490700 ps |
| T1091 |
/workspace/coverage/default/15.flash_ctrl_mp_regions.1887433401 |
|
|
Jul 15 07:33:49 PM PDT 24 |
Jul 15 07:39:16 PM PDT 24 |
44151077100 ps |
| T1092 |
/workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.825945560 |
|
|
Jul 15 07:34:26 PM PDT 24 |
Jul 15 07:34:40 PM PDT 24 |
16051300 ps |
| T1093 |
/workspace/coverage/default/5.flash_ctrl_hw_sec_otp.1363634430 |
|
|
Jul 15 07:31:55 PM PDT 24 |
Jul 15 07:36:05 PM PDT 24 |
3100006200 ps |
| T1094 |
/workspace/coverage/default/49.flash_ctrl_connect.3412587508 |
|
|
Jul 15 07:36:51 PM PDT 24 |
Jul 15 07:37:09 PM PDT 24 |
16171500 ps |
| T1095 |
/workspace/coverage/default/0.flash_ctrl_disable.4010510154 |
|
|
Jul 15 07:31:09 PM PDT 24 |
Jul 15 07:31:41 PM PDT 24 |
20826900 ps |
| T397 |
/workspace/coverage/default/41.flash_ctrl_disable.67722843 |
|
|
Jul 15 07:36:25 PM PDT 24 |
Jul 15 07:36:48 PM PDT 24 |
11337600 ps |
| T302 |
/workspace/coverage/default/0.flash_ctrl_wr_intg.191840854 |
|
|
Jul 15 07:31:09 PM PDT 24 |
Jul 15 07:31:34 PM PDT 24 |
325026300 ps |
| T1096 |
/workspace/coverage/default/0.flash_ctrl_rw_evict.3369533978 |
|
|
Jul 15 07:31:00 PM PDT 24 |
Jul 15 07:31:45 PM PDT 24 |
86074400 ps |
| T1097 |
/workspace/coverage/default/11.flash_ctrl_mp_regions.1295130417 |
|
|
Jul 15 07:33:04 PM PDT 24 |
Jul 15 07:39:43 PM PDT 24 |
16664839000 ps |
| T1098 |
/workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.3035277858 |
|
|
Jul 15 07:31:51 PM PDT 24 |
Jul 15 07:33:14 PM PDT 24 |
10054549000 ps |
| T1099 |
/workspace/coverage/default/15.flash_ctrl_smoke.3069394456 |
|
|
Jul 15 07:33:50 PM PDT 24 |
Jul 15 07:37:13 PM PDT 24 |
748290200 ps |
| T1100 |
/workspace/coverage/default/7.flash_ctrl_error_mp.2666536780 |
|
|
Jul 15 07:32:16 PM PDT 24 |
Jul 15 08:14:28 PM PDT 24 |
5130740000 ps |
| T1101 |
/workspace/coverage/default/0.flash_ctrl_error_prog_win.2567158218 |
|
|
Jul 15 07:30:53 PM PDT 24 |
Jul 15 07:46:02 PM PDT 24 |
5868966000 ps |
| T1102 |
/workspace/coverage/default/1.flash_ctrl_error_prog_type.3165712538 |
|
|
Jul 15 07:31:07 PM PDT 24 |
Jul 15 08:19:02 PM PDT 24 |
2081349700 ps |
| T1103 |
/workspace/coverage/default/45.flash_ctrl_sec_info_access.4002516842 |
|
|
Jul 15 07:36:37 PM PDT 24 |
Jul 15 07:38:00 PM PDT 24 |
1852338200 ps |
| T1104 |
/workspace/coverage/default/8.flash_ctrl_ro_derr.744561727 |
|
|
Jul 15 07:32:31 PM PDT 24 |
Jul 15 07:35:39 PM PDT 24 |
2738532500 ps |
| T1105 |
/workspace/coverage/default/24.flash_ctrl_alert_test.1052489980 |
|
|
Jul 15 07:35:16 PM PDT 24 |
Jul 15 07:35:31 PM PDT 24 |
258937500 ps |
| T1106 |
/workspace/coverage/default/0.flash_ctrl_stress_all.1215156238 |
|
|
Jul 15 07:31:00 PM PDT 24 |
Jul 15 08:02:41 PM PDT 24 |
1068363500 ps |
| T1107 |
/workspace/coverage/default/39.flash_ctrl_otp_reset.640138938 |
|
|
Jul 15 07:36:25 PM PDT 24 |
Jul 15 07:38:17 PM PDT 24 |
33919300 ps |
| T1108 |
/workspace/coverage/default/2.flash_ctrl_smoke.3492130730 |
|
|
Jul 15 07:31:28 PM PDT 24 |
Jul 15 07:33:13 PM PDT 24 |
43606300 ps |
| T1109 |
/workspace/coverage/default/11.flash_ctrl_lcmgr_intg.1808520262 |
|
|
Jul 15 07:33:07 PM PDT 24 |
Jul 15 07:33:21 PM PDT 24 |
17860100 ps |
| T1110 |
/workspace/coverage/default/73.flash_ctrl_connect.3733370469 |
|
|
Jul 15 07:37:09 PM PDT 24 |
Jul 15 07:37:27 PM PDT 24 |
23260600 ps |
| T1111 |
/workspace/coverage/default/17.flash_ctrl_hw_rma_reset.2380715976 |
|
|
Jul 15 07:34:12 PM PDT 24 |
Jul 15 07:50:44 PM PDT 24 |
420277199200 ps |
| T1112 |
/workspace/coverage/default/9.flash_ctrl_rw_derr.375921763 |
|
|
Jul 15 07:32:43 PM PDT 24 |
Jul 15 07:42:28 PM PDT 24 |
13966636100 ps |
| T205 |
/workspace/coverage/default/0.flash_ctrl_phy_host_grant_err.4120913552 |
|
|
Jul 15 07:31:10 PM PDT 24 |
Jul 15 07:31:33 PM PDT 24 |
14989000 ps |
| T360 |
/workspace/coverage/default/16.flash_ctrl_re_evict.140123851 |
|
|
Jul 15 07:34:06 PM PDT 24 |
Jul 15 07:34:44 PM PDT 24 |
70120100 ps |
| T1113 |
/workspace/coverage/default/2.flash_ctrl_oversize_error.1572285711 |
|
|
Jul 15 07:31:22 PM PDT 24 |
Jul 15 07:35:09 PM PDT 24 |
5915666900 ps |
| T1114 |
/workspace/coverage/default/40.flash_ctrl_alert_test.26284693 |
|
|
Jul 15 07:36:25 PM PDT 24 |
Jul 15 07:36:40 PM PDT 24 |
122438500 ps |
| T1115 |
/workspace/coverage/default/0.flash_ctrl_serr_address.3538642854 |
|
|
Jul 15 07:30:54 PM PDT 24 |
Jul 15 07:32:22 PM PDT 24 |
10086944000 ps |
| T1116 |
/workspace/coverage/default/5.flash_ctrl_intr_wr.1004631811 |
|
|
Jul 15 07:31:49 PM PDT 24 |
Jul 15 07:33:04 PM PDT 24 |
2851877800 ps |
| T1117 |
/workspace/coverage/default/77.flash_ctrl_otp_reset.2087104922 |
|
|
Jul 15 07:37:17 PM PDT 24 |
Jul 15 07:39:31 PM PDT 24 |
42224400 ps |
| T1118 |
/workspace/coverage/default/29.flash_ctrl_intr_rd_slow_flash.1225220867 |
|
|
Jul 15 07:35:34 PM PDT 24 |
Jul 15 07:40:35 PM PDT 24 |
26023216700 ps |
| T1119 |
/workspace/coverage/default/41.flash_ctrl_hw_sec_otp.4038279939 |
|
|
Jul 15 07:36:24 PM PDT 24 |
Jul 15 07:39:01 PM PDT 24 |
9539957000 ps |
| T1120 |
/workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.2596535649 |
|
|
Jul 15 07:35:30 PM PDT 24 |
Jul 15 07:35:59 PM PDT 24 |
39200400 ps |
| T1121 |
/workspace/coverage/default/6.flash_ctrl_error_prog_win.951629087 |
|
|
Jul 15 07:31:55 PM PDT 24 |
Jul 15 07:45:39 PM PDT 24 |
1509554500 ps |
| T1122 |
/workspace/coverage/default/1.flash_ctrl_config_regwen.3722898708 |
|
|
Jul 15 07:31:24 PM PDT 24 |
Jul 15 07:31:43 PM PDT 24 |
34535300 ps |
| T1123 |
/workspace/coverage/default/4.flash_ctrl_hw_read_seed_err.1715288207 |
|
|
Jul 15 07:31:50 PM PDT 24 |
Jul 15 07:32:09 PM PDT 24 |
15606400 ps |
| T1124 |
/workspace/coverage/default/10.flash_ctrl_rand_ops.2856847938 |
|
|
Jul 15 07:32:49 PM PDT 24 |
Jul 15 07:37:21 PM PDT 24 |
187791200 ps |
| T1125 |
/workspace/coverage/default/60.flash_ctrl_connect.2771555777 |
|
|
Jul 15 07:36:58 PM PDT 24 |
Jul 15 07:37:13 PM PDT 24 |
14708100 ps |
| T1126 |
/workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.435298333 |
|
|
Jul 15 07:31:34 PM PDT 24 |
Jul 15 08:06:42 PM PDT 24 |
950953516200 ps |
| T1127 |
/workspace/coverage/default/0.flash_ctrl_sec_info_access.2917196182 |
|
|
Jul 15 07:31:08 PM PDT 24 |
Jul 15 07:32:15 PM PDT 24 |
904091100 ps |
| T1128 |
/workspace/coverage/default/1.flash_ctrl_rw_derr.1208457816 |
|
|
Jul 15 07:31:13 PM PDT 24 |
Jul 15 07:44:01 PM PDT 24 |
4502893500 ps |
| T429 |
/workspace/coverage/default/12.flash_ctrl_sec_info_access.3358818060 |
|
|
Jul 15 07:33:21 PM PDT 24 |
Jul 15 07:34:29 PM PDT 24 |
1239708800 ps |
| T1129 |
/workspace/coverage/default/45.flash_ctrl_smoke.543518676 |
|
|
Jul 15 07:36:39 PM PDT 24 |
Jul 15 07:37:53 PM PDT 24 |
182305800 ps |
| T63 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2093458763 |
|
|
Jul 15 07:26:17 PM PDT 24 |
Jul 15 07:26:59 PM PDT 24 |
93961900 ps |
| T64 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2251172126 |
|
|
Jul 15 07:25:56 PM PDT 24 |
Jul 15 07:26:54 PM PDT 24 |
35468900 ps |
| T65 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2912751181 |
|
|
Jul 15 07:26:23 PM PDT 24 |
Jul 15 07:27:03 PM PDT 24 |
367202400 ps |
| T263 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.4158818370 |
|
|
Jul 15 07:26:24 PM PDT 24 |
Jul 15 07:27:04 PM PDT 24 |
25611500 ps |
| T108 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3623344857 |
|
|
Jul 15 07:26:08 PM PDT 24 |
Jul 15 07:26:54 PM PDT 24 |
166099500 ps |
| T264 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3681093657 |
|
|
Jul 15 07:26:32 PM PDT 24 |
Jul 15 07:27:15 PM PDT 24 |
29115700 ps |
| T256 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.736560879 |
|
|
Jul 15 07:26:25 PM PDT 24 |
Jul 15 07:27:12 PM PDT 24 |
248045600 ps |
| T1130 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.145576658 |
|
|
Jul 15 07:26:11 PM PDT 24 |
Jul 15 07:26:55 PM PDT 24 |
13689500 ps |
| T257 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1910895514 |
|
|
Jul 15 07:26:15 PM PDT 24 |
Jul 15 07:27:04 PM PDT 24 |
182163800 ps |
| T1131 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.362416919 |
|
|
Jul 15 07:25:56 PM PDT 24 |
Jul 15 07:26:41 PM PDT 24 |
25470100 ps |
| T1132 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.448616739 |
|
|
Jul 15 07:25:55 PM PDT 24 |
Jul 15 07:26:43 PM PDT 24 |
17357400 ps |
| T1133 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1603168711 |
|
|
Jul 15 07:26:26 PM PDT 24 |
Jul 15 07:27:06 PM PDT 24 |
24503900 ps |
| T258 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1456502915 |
|
|
Jul 15 07:26:09 PM PDT 24 |
Jul 15 07:27:12 PM PDT 24 |
64906100 ps |
| T109 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.847173521 |
|
|
Jul 15 07:26:25 PM PDT 24 |
Jul 15 07:27:09 PM PDT 24 |
29359800 ps |
| T259 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3499209929 |
|
|
Jul 15 07:25:56 PM PDT 24 |
Jul 15 07:26:45 PM PDT 24 |
36385100 ps |
| T223 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2004386115 |
|
|
Jul 15 07:26:25 PM PDT 24 |
Jul 15 07:27:10 PM PDT 24 |
68122400 ps |
| T336 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.2076789944 |
|
|
Jul 15 07:26:09 PM PDT 24 |
Jul 15 07:26:51 PM PDT 24 |
25907300 ps |
| T337 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.4022722330 |
|
|
Jul 15 07:26:33 PM PDT 24 |
Jul 15 07:27:15 PM PDT 24 |
58747700 ps |
| T338 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.236392840 |
|
|
Jul 15 07:26:26 PM PDT 24 |
Jul 15 07:27:06 PM PDT 24 |
59061500 ps |
| T106 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.41223129 |
|
|
Jul 15 07:25:56 PM PDT 24 |
Jul 15 07:34:07 PM PDT 24 |
2553509900 ps |
| T107 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1640919719 |
|
|
Jul 15 07:25:57 PM PDT 24 |
Jul 15 07:26:46 PM PDT 24 |
173471400 ps |
| T1134 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3371870603 |
|
|
Jul 15 07:26:15 PM PDT 24 |
Jul 15 07:27:03 PM PDT 24 |
226239900 ps |
| T339 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3099776470 |
|
|
Jul 15 07:26:32 PM PDT 24 |
Jul 15 07:27:15 PM PDT 24 |
31124100 ps |
| T342 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1659346660 |
|
|
Jul 15 07:26:26 PM PDT 24 |
Jul 15 07:27:07 PM PDT 24 |
80831800 ps |
| T340 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2088343426 |
|
|
Jul 15 07:26:22 PM PDT 24 |
Jul 15 07:27:02 PM PDT 24 |
143085600 ps |
| T1135 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.4280905868 |
|
|
Jul 15 07:26:25 PM PDT 24 |
Jul 15 07:27:09 PM PDT 24 |
13510900 ps |
| T341 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2336412989 |
|
|
Jul 15 07:26:25 PM PDT 24 |
Jul 15 07:27:07 PM PDT 24 |
15633900 ps |
| T1136 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1925282956 |
|
|
Jul 15 07:26:07 PM PDT 24 |
Jul 15 07:26:53 PM PDT 24 |
13770900 ps |
| T311 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2502810004 |
|
|
Jul 15 07:26:10 PM PDT 24 |
Jul 15 07:26:54 PM PDT 24 |
141252000 ps |
| T241 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.799835287 |
|
|
Jul 15 07:25:56 PM PDT 24 |
Jul 15 07:39:11 PM PDT 24 |
669419700 ps |
| T317 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3772166101 |
|
|
Jul 15 07:26:03 PM PDT 24 |
Jul 15 07:27:20 PM PDT 24 |
182352500 ps |
| T304 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1572659403 |
|
|
Jul 15 07:26:01 PM PDT 24 |
Jul 15 07:27:16 PM PDT 24 |
1461479400 ps |
| T319 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.4252066050 |
|
|
Jul 15 07:26:24 PM PDT 24 |
Jul 15 07:27:07 PM PDT 24 |
188839000 ps |
| T242 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2159468105 |
|
|
Jul 15 07:25:59 PM PDT 24 |
Jul 15 07:26:45 PM PDT 24 |
17692200 ps |
| T236 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.364982783 |
|
|
Jul 15 07:26:00 PM PDT 24 |
Jul 15 07:26:48 PM PDT 24 |
71274500 ps |
| T1137 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2641529124 |
|
|
Jul 15 07:26:25 PM PDT 24 |
Jul 15 07:27:06 PM PDT 24 |
52393700 ps |
| T1138 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.523727115 |
|
|
Jul 15 07:26:10 PM PDT 24 |
Jul 15 07:26:56 PM PDT 24 |
13816400 ps |
| T1139 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2084977918 |
|
|
Jul 15 07:26:18 PM PDT 24 |
Jul 15 07:27:02 PM PDT 24 |
12628200 ps |
| T237 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1108589420 |
|
|
Jul 15 07:26:01 PM PDT 24 |
Jul 15 07:26:51 PM PDT 24 |
113989700 ps |
| T1140 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.868554769 |
|
|
Jul 15 07:26:33 PM PDT 24 |
Jul 15 07:27:15 PM PDT 24 |
15822100 ps |
| T318 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.4238586781 |
|
|
Jul 15 07:26:27 PM PDT 24 |
Jul 15 07:27:11 PM PDT 24 |
223887100 ps |
| T238 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.314129419 |
|
|
Jul 15 07:26:23 PM PDT 24 |
Jul 15 07:27:08 PM PDT 24 |
106850500 ps |
| T239 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1534954517 |
|
|
Jul 15 07:26:11 PM PDT 24 |
Jul 15 07:26:56 PM PDT 24 |
46991100 ps |
| T1141 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1693307963 |
|
|
Jul 15 07:26:17 PM PDT 24 |
Jul 15 07:26:58 PM PDT 24 |
179709800 ps |
| T1142 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.16860794 |
|
|
Jul 15 07:26:11 PM PDT 24 |
Jul 15 07:26:54 PM PDT 24 |
44405200 ps |
| T392 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.868805087 |
|
|
Jul 15 07:25:58 PM PDT 24 |
Jul 15 07:27:41 PM PDT 24 |
8807425300 ps |
| T1143 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1261412066 |
|
|
Jul 15 07:26:10 PM PDT 24 |
Jul 15 07:26:53 PM PDT 24 |
15040100 ps |
| T1144 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1137251922 |
|
|
Jul 15 07:26:08 PM PDT 24 |
Jul 15 07:26:52 PM PDT 24 |
15601700 ps |
| T1145 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2909703073 |
|
|
Jul 15 07:26:09 PM PDT 24 |
Jul 15 07:26:56 PM PDT 24 |
69444800 ps |
| T1146 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3184214946 |
|
|
Jul 15 07:25:55 PM PDT 24 |
Jul 15 07:27:07 PM PDT 24 |
642964000 ps |
| T1147 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1886820698 |
|
|
Jul 15 07:26:25 PM PDT 24 |
Jul 15 07:27:09 PM PDT 24 |
72345400 ps |
| T1148 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3449164342 |
|
|
Jul 15 07:26:18 PM PDT 24 |
Jul 15 07:26:59 PM PDT 24 |
29258900 ps |
| T243 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2707284975 |
|
|
Jul 15 07:26:02 PM PDT 24 |
Jul 15 07:26:47 PM PDT 24 |
48735000 ps |
| T449 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3554502806 |
|
|
Jul 15 07:25:54 PM PDT 24 |
Jul 15 07:27:19 PM PDT 24 |
1715508800 ps |
| T240 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3900590871 |
|
|
Jul 15 07:26:20 PM PDT 24 |
Jul 15 07:27:05 PM PDT 24 |
193793800 ps |
| T305 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.4183590043 |
|
|
Jul 15 07:26:14 PM PDT 24 |
Jul 15 07:27:02 PM PDT 24 |
913902500 ps |
| T254 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.589439443 |
|
|
Jul 15 07:26:28 PM PDT 24 |
Jul 15 07:34:34 PM PDT 24 |
388657900 ps |
| T1149 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.203911161 |
|
|
Jul 15 07:26:28 PM PDT 24 |
Jul 15 07:27:08 PM PDT 24 |
12741900 ps |
| T1150 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.3534654534 |
|
|
Jul 15 07:26:27 PM PDT 24 |
Jul 15 07:27:06 PM PDT 24 |
43394500 ps |
| T1151 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.1584402376 |
|
|
Jul 15 07:26:03 PM PDT 24 |
Jul 15 07:26:48 PM PDT 24 |
15513100 ps |
| T1152 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2557545899 |
|
|
Jul 15 07:26:21 PM PDT 24 |
Jul 15 07:27:04 PM PDT 24 |
24003200 ps |
| T1153 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.3710102912 |
|
|
Jul 15 07:26:03 PM PDT 24 |
Jul 15 07:26:47 PM PDT 24 |
49685700 ps |
| T1154 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.1166363607 |
|
|
Jul 15 07:26:32 PM PDT 24 |
Jul 15 07:27:14 PM PDT 24 |
46655900 ps |
| T260 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2901370313 |
|
|
Jul 15 07:26:10 PM PDT 24 |
Jul 15 07:26:59 PM PDT 24 |
115574100 ps |
| T1155 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1843231905 |
|
|
Jul 15 07:26:15 PM PDT 24 |
Jul 15 07:26:58 PM PDT 24 |
49307300 ps |
| T1156 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.837261452 |
|
|
Jul 15 07:26:23 PM PDT 24 |
Jul 15 07:27:19 PM PDT 24 |
97957800 ps |
| T1157 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.400263382 |
|
|
Jul 15 07:25:54 PM PDT 24 |
Jul 15 07:26:41 PM PDT 24 |
101395300 ps |
| T1158 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3667519483 |
|
|
Jul 15 07:26:28 PM PDT 24 |
Jul 15 07:27:12 PM PDT 24 |
107759600 ps |
| T1159 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.365430241 |
|
|
Jul 15 07:26:32 PM PDT 24 |
Jul 15 07:27:15 PM PDT 24 |
15658200 ps |
| T1160 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.1132933442 |
|
|
Jul 15 07:26:10 PM PDT 24 |
Jul 15 07:26:53 PM PDT 24 |
18653400 ps |
| T1161 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1858251485 |
|
|
Jul 15 07:26:32 PM PDT 24 |
Jul 15 07:27:14 PM PDT 24 |
39921700 ps |
| T306 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3510989817 |
|
|
Jul 15 07:26:01 PM PDT 24 |
Jul 15 07:26:48 PM PDT 24 |
596346700 ps |
| T307 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1032246162 |
|
|
Jul 15 07:26:23 PM PDT 24 |
Jul 15 07:27:05 PM PDT 24 |
104228700 ps |
| T270 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.40960515 |
|
|
Jul 15 07:26:20 PM PDT 24 |
Jul 15 07:33:17 PM PDT 24 |
350002400 ps |
| T1162 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2402403209 |
|
|
Jul 15 07:25:56 PM PDT 24 |
Jul 15 07:27:06 PM PDT 24 |
1284550800 ps |
| T310 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.370565498 |
|
|
Jul 15 07:26:20 PM PDT 24 |
Jul 15 07:27:03 PM PDT 24 |
463939200 ps |
| T308 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1725910083 |
|
|
Jul 15 07:25:57 PM PDT 24 |
Jul 15 07:27:03 PM PDT 24 |
710923200 ps |
| T1163 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.127564137 |
|
|
Jul 15 07:25:50 PM PDT 24 |
Jul 15 07:26:37 PM PDT 24 |
14369100 ps |
| T1164 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2334674101 |
|
|
Jul 15 07:26:21 PM PDT 24 |
Jul 15 07:27:08 PM PDT 24 |
64833500 ps |
| T1165 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2371913728 |
|
|
Jul 15 07:26:27 PM PDT 24 |
Jul 15 07:27:06 PM PDT 24 |
73318900 ps |
| T1166 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2242795436 |
|
|
Jul 15 07:26:32 PM PDT 24 |
Jul 15 07:27:15 PM PDT 24 |
17969300 ps |
| T1167 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.2044344373 |
|
|
Jul 15 07:26:33 PM PDT 24 |
Jul 15 07:27:15 PM PDT 24 |
35750100 ps |
| T309 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3678770568 |
|
|
Jul 15 07:26:04 PM PDT 24 |
Jul 15 07:27:44 PM PDT 24 |
3513106700 ps |
| T1168 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.351264631 |
|
|
Jul 15 07:26:19 PM PDT 24 |
Jul 15 07:26:59 PM PDT 24 |
113133300 ps |
| T244 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.47412205 |
|
|
Jul 15 07:25:54 PM PDT 24 |
Jul 15 07:26:41 PM PDT 24 |
34027400 ps |
| T1169 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1077283921 |
|
|
Jul 15 07:26:34 PM PDT 24 |
Jul 15 07:27:18 PM PDT 24 |
15764800 ps |
| T1170 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.269683122 |
|
|
Jul 15 07:26:19 PM PDT 24 |
Jul 15 07:27:02 PM PDT 24 |
20156400 ps |
| T1171 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1077880663 |
|
|
Jul 15 07:26:32 PM PDT 24 |
Jul 15 07:27:14 PM PDT 24 |
61122400 ps |
| T1172 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.510801617 |
|
|
Jul 15 07:26:04 PM PDT 24 |
Jul 15 07:27:09 PM PDT 24 |
132928100 ps |
| T1173 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.2431334384 |
|
|
Jul 15 07:26:18 PM PDT 24 |
Jul 15 07:27:03 PM PDT 24 |
106235600 ps |
| T1174 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.419971886 |
|
|
Jul 15 07:26:09 PM PDT 24 |
Jul 15 07:26:53 PM PDT 24 |
17430900 ps |
| T1175 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3051828425 |
|
|
Jul 15 07:26:28 PM PDT 24 |
Jul 15 07:27:11 PM PDT 24 |
15864600 ps |
| T1176 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.785998651 |
|
|
Jul 15 07:26:25 PM PDT 24 |
Jul 15 07:27:09 PM PDT 24 |
22566900 ps |
| T267 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3842335659 |
|
|
Jul 15 07:26:18 PM PDT 24 |
Jul 15 07:27:03 PM PDT 24 |
95139800 ps |
| T1177 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3293976956 |
|
|
Jul 15 07:26:17 PM PDT 24 |
Jul 15 07:27:01 PM PDT 24 |
14826300 ps |
| T1178 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2007176704 |
|
|
Jul 15 07:26:08 PM PDT 24 |
Jul 15 07:26:55 PM PDT 24 |
26895500 ps |
| T312 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3527005524 |
|
|
Jul 15 07:25:56 PM PDT 24 |
Jul 15 07:26:45 PM PDT 24 |
224718300 ps |
| T1179 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1290026558 |
|
|
Jul 15 07:25:53 PM PDT 24 |
Jul 15 07:26:39 PM PDT 24 |
14568500 ps |
| T1180 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.257965733 |
|
|
Jul 15 07:26:38 PM PDT 24 |
Jul 15 07:27:22 PM PDT 24 |
43551800 ps |
| T313 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2057395482 |
|
|
Jul 15 07:26:15 PM PDT 24 |
Jul 15 07:41:50 PM PDT 24 |
904516200 ps |
| T1181 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1117527391 |
|
|
Jul 15 07:26:25 PM PDT 24 |
Jul 15 07:27:07 PM PDT 24 |
26960500 ps |
| T261 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.528820276 |
|
|
Jul 15 07:26:24 PM PDT 24 |
Jul 15 07:27:07 PM PDT 24 |
179526200 ps |
| T1182 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.4226374857 |
|
|
Jul 15 07:26:08 PM PDT 24 |
Jul 15 07:26:54 PM PDT 24 |
14465200 ps |
| T1183 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2712660803 |
|
|
Jul 15 07:26:01 PM PDT 24 |
Jul 15 07:26:44 PM PDT 24 |
65623900 ps |
| T262 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.3760067746 |
|
|
Jul 15 07:26:09 PM PDT 24 |
Jul 15 07:34:21 PM PDT 24 |
234799100 ps |
| T1184 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.56534439 |
|
|
Jul 15 07:26:17 PM PDT 24 |
Jul 15 07:26:59 PM PDT 24 |
54454300 ps |
| T1185 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.349833992 |
|
|
Jul 15 07:25:56 PM PDT 24 |
Jul 15 07:26:43 PM PDT 24 |
11977800 ps |
| T272 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3371960739 |
|
|
Jul 15 07:26:03 PM PDT 24 |
Jul 15 07:41:48 PM PDT 24 |
2883265200 ps |
| T1186 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.4088015039 |
|
|
Jul 15 07:25:55 PM PDT 24 |
Jul 15 07:26:41 PM PDT 24 |
25499900 ps |
| T1187 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1283364289 |
|
|
Jul 15 07:26:30 PM PDT 24 |
Jul 15 07:27:17 PM PDT 24 |
241900900 ps |
| T386 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.4142003108 |
|
|
Jul 15 07:26:23 PM PDT 24 |
Jul 15 07:33:17 PM PDT 24 |
434597100 ps |
| T265 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.227930193 |
|
|
Jul 15 07:26:23 PM PDT 24 |
Jul 15 07:27:07 PM PDT 24 |
149559900 ps |
| T1188 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3524732736 |
|
|
Jul 15 07:26:14 PM PDT 24 |
Jul 15 07:27:00 PM PDT 24 |
98981300 ps |
| T1189 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1492903383 |
|
|
Jul 15 07:26:34 PM PDT 24 |
Jul 15 07:27:17 PM PDT 24 |
16902300 ps |
| T1190 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3186421088 |
|
|
Jul 15 07:26:12 PM PDT 24 |
Jul 15 07:26:53 PM PDT 24 |
40392800 ps |
| T1191 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1933785848 |
|
|
Jul 15 07:26:28 PM PDT 24 |
Jul 15 07:27:15 PM PDT 24 |
60250900 ps |
| T382 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3293921893 |
|
|
Jul 15 07:26:03 PM PDT 24 |
Jul 15 07:41:56 PM PDT 24 |
888921100 ps |
| T269 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1371010899 |
|
|
Jul 15 07:26:28 PM PDT 24 |
Jul 15 07:27:16 PM PDT 24 |
100509400 ps |
| T268 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3984553125 |
|
|
Jul 15 07:26:04 PM PDT 24 |
Jul 15 07:26:52 PM PDT 24 |
167148000 ps |
| T1192 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1880549710 |
|
|
Jul 15 07:26:18 PM PDT 24 |
Jul 15 07:27:00 PM PDT 24 |
32301800 ps |
| T378 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3872505142 |
|
|
Jul 15 07:26:16 PM PDT 24 |
Jul 15 07:27:05 PM PDT 24 |
167479800 ps |
| T1193 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.836931381 |
|
|
Jul 15 07:26:24 PM PDT 24 |
Jul 15 07:27:04 PM PDT 24 |
17490800 ps |
| T273 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3199366296 |
|
|
Jul 15 07:25:57 PM PDT 24 |
Jul 15 07:26:46 PM PDT 24 |
155423500 ps |
| T1194 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2958382953 |
|
|
Jul 15 07:26:10 PM PDT 24 |
Jul 15 07:26:53 PM PDT 24 |
47083900 ps |
| T379 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3517727754 |
|
|
Jul 15 07:26:28 PM PDT 24 |
Jul 15 07:27:14 PM PDT 24 |
54170000 ps |
| T1195 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1411447092 |
|
|
Jul 15 07:26:29 PM PDT 24 |
Jul 15 07:27:10 PM PDT 24 |
16651100 ps |
| T1196 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1108412280 |
|
|
Jul 15 07:26:30 PM PDT 24 |
Jul 15 07:27:11 PM PDT 24 |
14647300 ps |
| T1197 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.850069472 |
|
|
Jul 15 07:26:03 PM PDT 24 |
Jul 15 07:26:51 PM PDT 24 |
637528900 ps |
| T274 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.283427726 |
|
|
Jul 15 07:26:05 PM PDT 24 |
Jul 15 07:26:54 PM PDT 24 |
194241100 ps |
| T1198 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.4173847854 |
|
|
Jul 15 07:26:24 PM PDT 24 |
Jul 15 07:27:08 PM PDT 24 |
82692800 ps |
| T1199 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3361105919 |
|
|
Jul 15 07:26:33 PM PDT 24 |
Jul 15 07:27:15 PM PDT 24 |
51444900 ps |
| T383 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.636760408 |
|
|
Jul 15 07:26:15 PM PDT 24 |
Jul 15 07:33:09 PM PDT 24 |
643277800 ps |
| T1200 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.707258706 |
|
|
Jul 15 07:26:09 PM PDT 24 |
Jul 15 07:26:56 PM PDT 24 |
197387800 ps |
| T1201 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.822558250 |
|
|
Jul 15 07:26:24 PM PDT 24 |
Jul 15 07:27:04 PM PDT 24 |
45503800 ps |
| T314 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3579496759 |
|
|
Jul 15 07:26:28 PM PDT 24 |
Jul 15 07:27:14 PM PDT 24 |
126595000 ps |
| T387 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2648326820 |
|
|
Jul 15 07:26:10 PM PDT 24 |
Jul 15 07:41:42 PM PDT 24 |
357318700 ps |
| T384 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.419688208 |
|
|
Jul 15 07:26:16 PM PDT 24 |
Jul 15 07:41:36 PM PDT 24 |
1293047900 ps |
| T1202 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.89342109 |
|
|
Jul 15 07:26:09 PM PDT 24 |
Jul 15 07:26:54 PM PDT 24 |
22088200 ps |
| T1203 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.987270236 |
|
|
Jul 15 07:26:24 PM PDT 24 |
Jul 15 07:27:08 PM PDT 24 |
152873800 ps |
| T1204 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.1102871567 |
|
|
Jul 15 07:26:32 PM PDT 24 |
Jul 15 07:27:14 PM PDT 24 |
24976400 ps |
| T1205 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2030317747 |
|
|
Jul 15 07:25:55 PM PDT 24 |
Jul 15 07:26:43 PM PDT 24 |
11750000 ps |
| T1206 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.336949998 |
|
|
Jul 15 07:26:15 PM PDT 24 |
Jul 15 07:27:00 PM PDT 24 |
12984800 ps |
| T1207 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3740217874 |
|
|
Jul 15 07:25:55 PM PDT 24 |
Jul 15 07:26:44 PM PDT 24 |
54058400 ps |
| T1208 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2377076742 |
|
|
Jul 15 07:26:27 PM PDT 24 |
Jul 15 07:27:11 PM PDT 24 |
18481400 ps |
| T1209 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3473172104 |
|
|
Jul 15 07:25:57 PM PDT 24 |
Jul 15 07:27:15 PM PDT 24 |
50663500 ps |
| T1210 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3182989627 |
|
|
Jul 15 07:26:18 PM PDT 24 |
Jul 15 07:27:02 PM PDT 24 |
73388600 ps |
| T388 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3976780698 |
|
|
Jul 15 07:26:01 PM PDT 24 |
Jul 15 07:34:15 PM PDT 24 |
431353500 ps |
| T380 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3745079199 |
|
|
Jul 15 07:26:10 PM PDT 24 |
Jul 15 07:26:56 PM PDT 24 |
133078000 ps |
| T315 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1856026803 |
|
|
Jul 15 07:26:04 PM PDT 24 |
Jul 15 07:26:53 PM PDT 24 |
98401100 ps |
| T1211 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3422051153 |
|
|
Jul 15 07:26:32 PM PDT 24 |
Jul 15 07:27:14 PM PDT 24 |
15162900 ps |
| T1212 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1353716289 |
|
|
Jul 15 07:26:01 PM PDT 24 |
Jul 15 07:27:29 PM PDT 24 |
1339078100 ps |
| T1213 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1060985542 |
|
|
Jul 15 07:26:09 PM PDT 24 |
Jul 15 07:26:53 PM PDT 24 |
127013000 ps |
| T1214 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1573834651 |
|
|
Jul 15 07:26:28 PM PDT 24 |
Jul 15 07:27:13 PM PDT 24 |
101224300 ps |
| T1215 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1717177107 |
|
|
Jul 15 07:26:24 PM PDT 24 |
Jul 15 07:27:06 PM PDT 24 |
13289100 ps |
| T1216 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.4213653457 |
|
|
Jul 15 07:26:25 PM PDT 24 |
Jul 15 07:27:10 PM PDT 24 |
25175300 ps |
| T1217 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2852036685 |
|
|
Jul 15 07:26:10 PM PDT 24 |
Jul 15 07:26:53 PM PDT 24 |
55902600 ps |
| T1218 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.868944455 |
|
|
Jul 15 07:26:07 PM PDT 24 |
Jul 15 07:26:52 PM PDT 24 |
16661000 ps |
| T1219 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.971130953 |
|
|
Jul 15 07:26:30 PM PDT 24 |
Jul 15 07:27:11 PM PDT 24 |
29067300 ps |
| T1220 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.762887512 |
|
|
Jul 15 07:26:31 PM PDT 24 |
Jul 15 07:27:12 PM PDT 24 |
15149800 ps |
| T1221 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2411122361 |
|
|
Jul 15 07:26:13 PM PDT 24 |
Jul 15 07:27:01 PM PDT 24 |
88053300 ps |
| T1222 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.742249389 |
|
|
Jul 15 07:26:09 PM PDT 24 |
Jul 15 07:26:54 PM PDT 24 |
141035600 ps |
| T1223 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2817006720 |
|
|
Jul 15 07:26:11 PM PDT 24 |
Jul 15 07:26:58 PM PDT 24 |
55980000 ps |
| T316 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1169338224 |
|
|
Jul 15 07:26:23 PM PDT 24 |
Jul 15 07:27:08 PM PDT 24 |
457385800 ps |
| T1224 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2294198685 |
|
|
Jul 15 07:26:07 PM PDT 24 |
Jul 15 07:26:50 PM PDT 24 |
14688100 ps |
| T1225 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.311518968 |
|
|
Jul 15 07:26:29 PM PDT 24 |
Jul 15 07:27:11 PM PDT 24 |
13890600 ps |
| T1226 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.471931317 |
|
|
Jul 15 07:26:33 PM PDT 24 |
Jul 15 07:27:16 PM PDT 24 |
27081500 ps |
| T1227 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2085779716 |
|
|
Jul 15 07:26:24 PM PDT 24 |
Jul 15 07:27:07 PM PDT 24 |
36395100 ps |
| T1228 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2261029945 |
|
|
Jul 15 07:26:06 PM PDT 24 |
Jul 15 07:27:46 PM PDT 24 |
6528674200 ps |
| T1229 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.4179094516 |
|
|
Jul 15 07:25:55 PM PDT 24 |
Jul 15 07:26:41 PM PDT 24 |
32094000 ps |
| T1230 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1474431612 |
|
|
Jul 15 07:26:35 PM PDT 24 |
Jul 15 07:27:17 PM PDT 24 |
34162900 ps |
| T1231 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.46581084 |
|
|
Jul 15 07:25:55 PM PDT 24 |
Jul 15 07:26:43 PM PDT 24 |
272680500 ps |
| T275 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.749039299 |
|
|
Jul 15 07:26:21 PM PDT 24 |
Jul 15 07:41:57 PM PDT 24 |
355213400 ps |
| T1232 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3284454814 |
|
|
Jul 15 07:26:31 PM PDT 24 |
Jul 15 07:27:32 PM PDT 24 |
120580600 ps |
| T1233 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2001137649 |
|
|
Jul 15 07:26:11 PM PDT 24 |
Jul 15 07:26:54 PM PDT 24 |
12061800 ps |
| T1234 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3676050721 |
|
|
Jul 15 07:26:08 PM PDT 24 |
Jul 15 07:26:57 PM PDT 24 |
119932800 ps |
| T271 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.898169477 |
|
|
Jul 15 07:25:49 PM PDT 24 |
Jul 15 07:26:40 PM PDT 24 |
34515200 ps |
| T1235 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.970208882 |
|
|
Jul 15 07:26:10 PM PDT 24 |
Jul 15 07:26:55 PM PDT 24 |
14870300 ps |
| T1236 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2530937462 |
|
|
Jul 15 07:25:55 PM PDT 24 |
Jul 15 07:26:44 PM PDT 24 |
92928300 ps |
| T1237 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2124954327 |
|
|
Jul 15 07:25:55 PM PDT 24 |
Jul 15 07:26:41 PM PDT 24 |
86948100 ps |
| T1238 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1807313053 |
|
|
Jul 15 07:26:37 PM PDT 24 |
Jul 15 07:27:19 PM PDT 24 |
32123500 ps |
| T1239 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1351925136 |
|
|
Jul 15 07:26:05 PM PDT 24 |
Jul 15 07:26:49 PM PDT 24 |
18289700 ps |
| T1240 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1453304250 |
|
|
Jul 15 07:26:24 PM PDT 24 |
Jul 15 07:27:05 PM PDT 24 |
182926700 ps |
| T1241 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.440304388 |
|
|
Jul 15 07:26:29 PM PDT 24 |
Jul 15 07:27:15 PM PDT 24 |
153612900 ps |
| T1242 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2149402605 |
|
|
Jul 15 07:25:54 PM PDT 24 |
Jul 15 07:26:58 PM PDT 24 |
53190900 ps |
| T1243 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2913808409 |
|
|
Jul 15 07:26:08 PM PDT 24 |
Jul 15 07:26:51 PM PDT 24 |
13691800 ps |
| T1244 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1810760664 |
|
|
Jul 15 07:26:37 PM PDT 24 |
Jul 15 07:27:21 PM PDT 24 |
17089100 ps |
| T1245 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2969787740 |
|
|
Jul 15 07:26:24 PM PDT 24 |
Jul 15 07:27:06 PM PDT 24 |
23063800 ps |
| T389 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1269091891 |
|
|
Jul 15 07:26:25 PM PDT 24 |
Jul 15 07:33:16 PM PDT 24 |
329441900 ps |
| T1246 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.811666207 |
|
|
Jul 15 07:26:26 PM PDT 24 |
Jul 15 07:27:08 PM PDT 24 |
36431800 ps |
| T1247 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2308375661 |
|
|
Jul 15 07:26:18 PM PDT 24 |
Jul 15 07:34:27 PM PDT 24 |
2315645200 ps |
| T1248 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.4292124502 |
|
|
Jul 15 07:26:10 PM PDT 24 |
Jul 15 07:26:58 PM PDT 24 |
160233200 ps |
| T1249 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2201544869 |
|
|
Jul 15 07:26:24 PM PDT 24 |
Jul 15 07:27:10 PM PDT 24 |
231331200 ps |
| T266 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3404936739 |
|
|
Jul 15 07:25:57 PM PDT 24 |
Jul 15 07:34:16 PM PDT 24 |
382726300 ps |
| T1250 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1585945233 |
|
|
Jul 15 07:26:21 PM PDT 24 |
Jul 15 07:27:05 PM PDT 24 |
25584500 ps |
| T1251 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.173818472 |
|
|
Jul 15 07:25:57 PM PDT 24 |
Jul 15 07:26:44 PM PDT 24 |
213418900 ps |
| T1252 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.69533786 |
|
|
Jul 15 07:26:11 PM PDT 24 |
Jul 15 07:26:54 PM PDT 24 |
22769100 ps |
| T1253 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3069869098 |
|
|
Jul 15 07:26:12 PM PDT 24 |
Jul 15 07:26:56 PM PDT 24 |
23392400 ps |
| T1254 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1781495904 |
|
|
Jul 15 07:26:26 PM PDT 24 |
Jul 15 07:27:06 PM PDT 24 |
48900500 ps |