Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	390229	1		T1	2		T2	1		T3	1
all_values[1]	390229	1		T1	2		T2	1		T3	1
all_values[2]	390229	1		T1	2		T2	1		T3	1
all_values[3]	390229	1		T1	2		T2	1		T3	1
all_values[4]	390229	1		T1	2		T2	1		T3	1
all_values[5]	390229	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	786690	1		T1	12		T2	6		T3	6
auto[1]	1554684	1		T20	33424		T25	6564		T32	5184

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1147173	1		T1	7		T2	4		T3	4
auto[1]	1194201	1		T1	5		T2	2		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	390084	1		T1	2		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	145	1		T258	5		T259	4		T260	2
all_values[1]	auto[0]	auto[1]	390059	1		T1	2		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	170	1		T258	2		T260	6		T325	1
all_values[2]	auto[0]	auto[0]	1589	1		T1	2		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	77	1		T258	2		T259	2		T260	4
all_values[2]	auto[1]	auto[0]	388522	1		T20	8356		T25	1641		T32	1296
all_values[2]	auto[1]	auto[1]	41	1		T258	2		T259	1		T260	1
all_values[3]	auto[0]	auto[0]	1574	1		T1	2		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	50	1		T258	2		T259	1		T326	1
all_values[3]	auto[1]	auto[0]	93682	1		T20	226		T25	1641		T32	295
all_values[3]	auto[1]	auto[1]	294923	1		T20	8130		T32	1001		T33	1784
all_values[4]	auto[0]	auto[0]	1117	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	511	1		T1	1		T18	1		T4	1
all_values[4]	auto[1]	auto[0]	270631	1		T20	6736		T25	1		T32	948
all_values[4]	auto[1]	auto[1]	117970	1		T20	1620		T25	1640		T32	348
all_values[5]	auto[0]	auto[0]	1523	1		T1	2		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	106	1		T4	1		T34	1		T35	1
all_values[5]	auto[1]	auto[0]	388535	1		T20	8356		T25	1641		T32	1296
all_values[5]	auto[1]	auto[1]	65	1		T260	2		T325	1		T339	1