Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	259944	1		T1	3		T2	5		T16	3
auto[FlashEraseBank]	283315	1		T1	1		T2	6		T3	1

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	274705	1		T1	2		T2	10		T16	7
auto[FlashOpProgram]	248599	1		T1	2		T2	1		T3	1
auto[FlashOpErase]	15955	1		T18	1		T11	10		T28	11
auto[FlashOpInvalid]	4000	1		T72	200		T74	200		T207	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	274705	1		T1	2		T2	10		T16	7
op[FlashOpProgram]	248599	1		T1	2		T2	1		T3	1
op[FlashOpErase]	15955	1		T18	1		T11	10		T28	11
read_erase_read	564	1		T28	2		T5	1		T53	1
read_prog_read	823	1		T1	1		T2	1		T4	8

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	402097	1		T1	4		T2	1		T3	1
auto[FlashPartInfo]	137443	1		T2	9		T16	3		T4	376
auto[FlashPartInfo1]	848	1		T4	1		T38	10		T6	1
auto[FlashPartInfo2]	2871	1		T2	1		T4	14		T38	4

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	204097	1		T1	2		T2	1		T16	4
auto[FlashPartData]	auto[FlashOpProgram]	190447	1		T1	2		T3	1		T16	1
auto[FlashPartData]	auto[FlashOpErase]	3607	1		T18	1		T11	4		T38	1
auto[FlashPartData]	auto[FlashOpInvalid]	3946	1		T72	200		T74	196		T207	200
auto[FlashPartInfo]	auto[FlashOpRead]	68032	1		T2	8		T16	3		T4	259
auto[FlashPartInfo]	auto[FlashOpProgram]	57041	1		T2	1		T4	117		T11	192
auto[FlashPartInfo]	auto[FlashOpErase]	12322	1		T11	6		T28	11		T13	6
auto[FlashPartInfo]	auto[FlashOpInvalid]	48	1		T74	4		T414	2		T415	4
auto[FlashPartInfo1]	auto[FlashOpRead]	681	1		T4	1		T38	10		T6	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T56	32		T134	32		T137	32
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T139	1		T123	1		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T139	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1895	1		T2	1		T4	7		T6	6
auto[FlashPartInfo2]	auto[FlashOpProgram]	948	1		T4	7		T38	4		T6	4
auto[FlashPartInfo2]	auto[FlashOpErase]	24	1		T73	2		T131	1		T129	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	4	1		T139	2		T416	2		-	-