Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.86	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	3	29	90.62

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	3	29	90.62	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31588	1		T5	5		T13	8		T84	1
auto[1]	54	1		T54	9		T271	1		T343	11
auto[2]	36	1		T54	1		T145	2		T344	1
auto[3]	205	1		T2	1		T16	1		T24	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7980	1		T5	1		T13	2		T54	4
evic_idx[1]	7968	1		T5	1		T24	1		T13	2
evic_idx[2]	7969	1		T5	2		T13	2		T54	2
evic_idx[3]	7966	1		T2	1		T16	1		T5	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31007	1		T84	1		T54	14		T72	400
evic_op[2]	304	1		T2	1		T16	1		T5	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	3	29	90.62	3

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0] , evic_idx[1] , evic_idx[2]]	[evic_op[2]]	[auto[2]]	--	--	3

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7694	1		T72	100		T90	149		T73	1
evic_idx[0]	evic_op[1]	auto[1]	15	1		T54	3		T343	4		T345	1
evic_idx[0]	evic_op[1]	auto[2]	6	1		T145	1		T346	1		T345	2
evic_idx[0]	evic_op[1]	auto[3]	44	1		T54	1		T73	5		T131	6
evic_idx[0]	evic_op[2]	auto[0]	67	1		T55	4		T60	4		T193	2
evic_idx[0]	evic_op[2]	auto[1]	2	1		T271	1		T347	1		-	-
evic_idx[0]	evic_op[2]	auto[3]	9	1		T206	1		T143	1		T348	1
evic_idx[1]	evic_op[1]	auto[0]	7695	1		T72	100		T90	149		T73	1
evic_idx[1]	evic_op[1]	auto[1]	11	1		T54	1		T343	3		T349	3
evic_idx[1]	evic_op[1]	auto[2]	5	1		T54	1		T346	1		T345	2
evic_idx[1]	evic_op[1]	auto[3]	43	1		T54	3		T73	5		T131	3
evic_idx[1]	evic_op[2]	auto[0]	62	1		T55	4		T60	4		T193	2
evic_idx[1]	evic_op[2]	auto[1]	1	1		T350	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[3]	8	1		T24	1		T351	1		T352	1
evic_idx[2]	evic_op[1]	auto[0]	7692	1		T72	100		T90	149		T74	100
evic_idx[2]	evic_op[1]	auto[1]	13	1		T54	2		T343	2		T349	4
evic_idx[2]	evic_op[1]	auto[2]	3	1		T345	2		T353	1		-	-
evic_idx[2]	evic_op[1]	auto[3]	39	1		T73	3		T131	2		T354	2
evic_idx[2]	evic_op[2]	auto[0]	67	1		T5	1		T55	4		T60	4
evic_idx[2]	evic_op[2]	auto[1]	1	1		T355	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[3]	11	1		T356	1		T357	1		T358	1
evic_idx[3]	evic_op[1]	auto[0]	7694	1		T84	1		T72	100		T90	149
evic_idx[3]	evic_op[1]	auto[1]	9	1		T54	3		T343	2		T349	2
evic_idx[3]	evic_op[1]	auto[2]	5	1		T145	1		T346	1		T345	2
evic_idx[3]	evic_op[1]	auto[3]	39	1		T73	3		T131	3		T354	3
evic_idx[3]	evic_op[2]	auto[0]	61	1		T55	4		T60	4		T193	2
evic_idx[3]	evic_op[2]	auto[1]	2	1		T359	1		T360	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	1	1		T344	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[3]	12	1		T2	1		T16	1		T50	1