Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

---

Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	45542	1		T82	13744		T330	947		T331	15474
rd_lvl[2]	71432	1		T182	560		T82	9924		T330	246
rd_lvl[3]	9913	1		T20	1309		T182	51		T330	1
rd_lvl[4]	24683	1		T20	5673		T182	2		T330	2
rd_lvl[5]	10976	1		T20	977		T32	629		T332	2338
rd_lvl[6]	11435	1		T32	210		T268	2860		T332	1244
rd_lvl[7]	5476	1		T32	8		T268	485		T333	516
rd_lvl[8]	14882	1		T32	43		T333	269		T200	9
rd_lvl[9]	7239	1		T334	651		T333	206		T200	24
rd_lvl[10]	11107	1		T335	1361		T334	989		T272	1093
rd_lvl[11]	4427	1		T32	43		T335	354		T272	408
rd_lvl[12]	10147	1		T29	614		T31	332		T336	1230
rd_lvl[13]	6494	1		T33	712		T29	200		T31	189
rd_lvl[14]	9145	1		T33	1072		T337	1284		T338	60
rd_lvl[15]	2295	1		T29	1		T30	232		T31	45