Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	390229	1		T1	2		T2	1		T3	1
all_pins[1]	390229	1		T1	2		T2	1		T3	1
all_pins[2]	390229	1		T1	2		T2	1		T3	1
all_pins[3]	390229	1		T1	2		T2	1		T3	1
all_pins[4]	390229	1		T1	2		T2	1		T3	1
all_pins[5]	390229	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1965191	1		T1	12		T2	6		T3	6
values[0x1]	376183	1		T20	9617		T25	1640		T32	1335
transitions[0x0=>0x1]	342279	1		T20	8203		T25	1640		T32	1228
transitions[0x1=>0x0]	342270	1		T20	8203		T25	1640		T32	1228

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	390084	1		T1	2		T2	1		T3	1
all_pins[0]	values[0x1]	145	1		T258	5		T259	4		T260	2
all_pins[0]	transitions[0x0=>0x1]	71	1		T258	3		T259	4		T260	1
all_pins[0]	transitions[0x1=>0x0]	96	1		T260	5		T325	1		T326	3
all_pins[1]	values[0x0]	390059	1		T1	2		T2	1		T3	1
all_pins[1]	values[0x1]	170	1		T258	2		T260	6		T325	1
all_pins[1]	transitions[0x0=>0x1]	146	1		T258	2		T260	6		T325	1
all_pins[1]	transitions[0x1=>0x0]	2377	1		T30	840		T361	125		T362	99
all_pins[2]	values[0x0]	387828	1		T1	2		T2	1		T3	1
all_pins[2]	values[0x1]	2401	1		T30	840		T361	125		T362	99
all_pins[2]	transitions[0x0=>0x1]	30	1		T258	2		T259	1		T326	2
all_pins[2]	transitions[0x1=>0x0]	245934	1		T20	7959		T32	933		T33	1784
all_pins[3]	values[0x0]	141924	1		T1	2		T2	1		T3	1
all_pins[3]	values[0x1]	248305	1		T20	7959		T32	933		T33	1784
all_pins[3]	transitions[0x0=>0x1]	216917	1		T20	6545		T32	826		T33	1784
all_pins[3]	transitions[0x1=>0x0]	93709	1		T20	244		T25	1640		T32	295
all_pins[4]	values[0x0]	265132	1		T1	2		T2	1		T3	1
all_pins[4]	values[0x1]	125097	1		T20	1658		T25	1640		T32	402
all_pins[4]	transitions[0x0=>0x1]	125082	1		T20	1658		T25	1640		T32	402
all_pins[4]	transitions[0x1=>0x0]	50	1		T260	2		T339	1		T329	3
all_pins[5]	values[0x0]	390164	1		T1	2		T2	1		T3	1
all_pins[5]	values[0x1]	65	1		T260	2		T325	1		T339	1
all_pins[5]	transitions[0x0=>0x1]	33	1		T260	2		T339	1		T329	2
all_pins[5]	transitions[0x1=>0x0]	104	1		T258	5		T259	3		T260	2