Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	398068	1		T1	2		T2	1		T3	2
all_values[1]	398068	1		T1	2		T2	1		T3	2
all_values[2]	398068	1		T1	2		T2	1		T3	2
all_values[3]	398068	1		T1	2		T2	1		T3	2
all_values[4]	398068	1		T1	2		T2	1		T3	2
all_values[5]	398068	1		T1	2		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	802270	1		T1	12		T2	6		T3	12
auto[1]	1586138	1		T5	12944		T6	25600		T22	19764

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1174668	1		T1	7		T2	4		T3	7
auto[1]	1213740	1		T1	5		T2	2		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	397921	1		T1	2		T2	1		T3	2
all_values[0]	auto[1]	auto[1]	147	1		T245	4		T246	1		T306	2
all_values[1]	auto[0]	auto[1]	397917	1		T1	2		T2	1		T3	2
all_values[1]	auto[1]	auto[1]	151	1		T245	2		T246	3		T306	5
all_values[2]	auto[0]	auto[0]	1551	1		T1	2		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	54	1		T245	1		T246	1		T306	3
all_values[2]	auto[1]	auto[0]	396405	1		T5	3236		T6	6400		T22	4941
all_values[2]	auto[1]	auto[1]	58	1		T245	1		T306	1		T307	3
all_values[3]	auto[0]	auto[0]	1556	1		T1	2		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	48	1		T245	1		T246	1		T307	2
all_values[3]	auto[1]	auto[0]	84436	1		T5	1618		T22	1647		T31	64
all_values[3]	auto[1]	auto[1]	312028	1		T5	1618		T6	6400		T22	3294
all_values[4]	auto[0]	auto[0]	1106	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	506	1		T1	1		T3	1		T4	1
all_values[4]	auto[1]	auto[0]	291721	1		T5	1618		T6	4800		T22	3294
all_values[4]	auto[1]	auto[1]	104735	1		T5	1618		T6	1600		T22	1647
all_values[5]	auto[0]	auto[0]	1505	1		T1	2		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	106	1		T42	1		T44	1		T102	1
all_values[5]	auto[1]	auto[0]	396388	1		T5	3236		T6	6400		T22	4941
all_values[5]	auto[1]	auto[1]	69	1		T246	1		T306	3		T307	3