Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	246043	1		T1	879		T2	790		T3	21
auto[FlashEraseBank]	270604	1		T1	687		T3	10		T4	1357

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	260441	1		T2	396		T3	17		T4	1688
auto[FlashOpProgram]	237136	1		T1	1566		T2	197		T3	13
auto[FlashOpErase]	15070	1		T2	197		T3	1		T10	5
auto[FlashOpInvalid]	4000	1		T197	200		T198	200		T199	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	260441	1		T2	396		T3	17		T4	1688
op[FlashOpProgram]	237136	1		T1	1566		T2	197		T3	13
op[FlashOpErase]	15070	1		T2	197		T3	1		T10	5
read_erase_read	565	1		T25	5		T28	15		T36	1
read_prog_read	855	1		T3	4		T4	12		T25	4

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	378935	1		T1	1330		T3	17		T4	2721
auto[FlashPartInfo]	134242	1		T1	232		T2	790		T3	5
auto[FlashPartInfo1]	777	1		T3	6		T4	1		T25	1
auto[FlashPartInfo2]	2693	1		T1	4		T3	3		T4	14

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	190696	1		T3	8		T4	1420		T10	128
auto[FlashPartData]	auto[FlashOpProgram]	180710	1		T1	1330		T3	9		T4	1301
auto[FlashPartData]	auto[FlashOpErase]	3621	1		T10	2		T25	34		T56	1
auto[FlashPartData]	auto[FlashOpInvalid]	3908	1		T197	198		T198	200		T199	194
auto[FlashPartInfo]	auto[FlashOpRead]	67400	1		T2	396		T3	1		T4	257
auto[FlashPartInfo]	auto[FlashOpProgram]	55352	1		T1	232		T2	197		T3	3
auto[FlashPartInfo]	auto[FlashOpErase]	11406	1		T2	197		T3	1		T10	3
auto[FlashPartInfo]	auto[FlashOpInvalid]	84	1		T197	2		T199	4		T408	2
auto[FlashPartInfo1]	auto[FlashOpRead]	611	1		T3	6		T4	1		T25	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	161	1		T132	32		T133	32		T409	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T115	1		T410	1		T411	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T411	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1734	1		T3	2		T4	10		T28	4
auto[FlashPartInfo2]	auto[FlashOpProgram]	913	1		T1	4		T3	1		T4	4
auto[FlashPartInfo2]	auto[FlashOpErase]	40	1		T28	3		T88	4		T263	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	6	1		T199	2		T412	2		T413	2