Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29587	1		T2	376		T25	28		T48	656
auto[1]	43	1		T103	2		T201	1		T328	1
auto[2]	78	1		T30	2		T88	9		T263	3
auto[3]	255	1		T28	24		T88	10		T263	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7492	1		T2	94		T25	7		T28	7
evic_idx[1]	7486	1		T2	94		T25	7		T28	6
evic_idx[2]	7498	1		T2	94		T25	7		T28	6
evic_idx[3]	7487	1		T2	94		T25	7		T28	5

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28972	1		T2	376		T28	24		T48	656
evic_op[2]	378	1		T72	36		T30	5		T40	2

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[1]]	[evic_op[2]]	[auto[1]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7171	1		T2	94		T48	164		T49	46
evic_idx[0]	evic_op[1]	auto[1]	12	1		T329	3		T330	2		T331	4
evic_idx[0]	evic_op[1]	auto[2]	12	1		T88	2		T263	1		T329	2
evic_idx[0]	evic_op[1]	auto[3]	52	1		T28	7		T88	2		T192	6
evic_idx[0]	evic_op[2]	auto[0]	79	1		T72	9		T30	1		T77	1
evic_idx[0]	evic_op[2]	auto[1]	1	1		T332	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[2]	3	1		T333	1		T334	1		T335	1
evic_idx[0]	evic_op[2]	auto[3]	8	1		T40	1		T336	1		T337	1
evic_idx[1]	evic_op[1]	auto[0]	7167	1		T2	94		T48	164		T49	46
evic_idx[1]	evic_op[1]	auto[1]	8	1		T329	1		T338	1		T330	2
evic_idx[1]	evic_op[1]	auto[2]	12	1		T88	2		T263	1		T339	1
evic_idx[1]	evic_op[1]	auto[3]	52	1		T28	6		T88	2		T192	5
evic_idx[1]	evic_op[2]	auto[0]	76	1		T72	9		T30	1		T77	1
evic_idx[1]	evic_op[2]	auto[2]	4	1		T30	1		T333	1		T340	1
evic_idx[1]	evic_op[2]	auto[3]	14	1		T40	1		T193	1		T341	1
evic_idx[2]	evic_op[1]	auto[0]	7169	1		T2	94		T48	164		T49	46
evic_idx[2]	evic_op[1]	auto[1]	8	1		T329	2		T338	1		T330	1
evic_idx[2]	evic_op[1]	auto[2]	16	1		T88	3		T329	2		T342	1
evic_idx[2]	evic_op[1]	auto[3]	52	1		T28	6		T88	3		T192	8
evic_idx[2]	evic_op[2]	auto[0]	77	1		T72	9		T77	1		T181	1
evic_idx[2]	evic_op[2]	auto[1]	5	1		T103	1		T328	1		T343	1
evic_idx[2]	evic_op[2]	auto[2]	4	1		T30	1		T344	1		T345	1
evic_idx[2]	evic_op[2]	auto[3]	14	1		T45	1		T346	1		T347	1
evic_idx[3]	evic_op[1]	auto[0]	7169	1		T2	94		T48	164		T49	46
evic_idx[3]	evic_op[1]	auto[1]	6	1		T329	2		T330	1		T331	2
evic_idx[3]	evic_op[1]	auto[2]	12	1		T88	2		T263	1		T329	2
evic_idx[3]	evic_op[1]	auto[3]	54	1		T28	5		T88	3		T263	1
evic_idx[3]	evic_op[2]	auto[0]	78	1		T72	9		T30	1		T77	1
evic_idx[3]	evic_op[2]	auto[1]	3	1		T103	1		T201	1		T348	1
evic_idx[3]	evic_op[2]	auto[2]	3	1		T349	1		T333	1		T345	1
evic_idx[3]	evic_op[2]	auto[3]	9	1		T350	1		T351	1		T352	1