Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	63166	1		T313	14286		T314	16603		T315	15220
rd_lvl[2]	48982	1		T316	1266		T265	2518		T313	10082
rd_lvl[3]	11705	1		T317	4320		T316	545		T265	2182
rd_lvl[4]	30131	1		T6	5525		T317	4080		T316	103
rd_lvl[5]	19095	1		T6	875		T210	2516		T316	431
rd_lvl[6]	26009	1		T22	2450		T210	2716		T316	478
rd_lvl[7]	9106	1		T22	470		T318	1975		T319	1723
rd_lvl[8]	9739	1		T318	1525		T319	1407		T320	1
rd_lvl[9]	4809	1		T321	493		T303	162		T322	110
rd_lvl[10]	5788	1		T5	1366		T31	49		T321	1042
rd_lvl[11]	4109	1		T5	252		T31	14		T211	156
rd_lvl[12]	8754	1		T211	1569		T38	184		T39	1076
rd_lvl[13]	4188	1		T31	1		T323	145		T316	54
rd_lvl[14]	6501	1		T38	19		T324	297		T325	1477
rd_lvl[15]	812	1		T323	130		T324	170		T326	35