Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	398068	1		T1	2		T2	1		T3	2
all_pins[1]	398068	1		T1	2		T2	1		T3	2
all_pins[2]	398068	1		T1	2		T2	1		T3	2
all_pins[3]	398068	1		T1	2		T2	1		T3	2
all_pins[4]	398068	1		T1	2		T2	1		T3	2
all_pins[5]	398068	1		T1	2		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2018649	1		T1	12		T2	6		T3	12
values[0x1]	369759	1		T5	3236		T6	8000		T22	4567
transitions[0x0=>0x1]	337942	1		T5	3236		T6	6400		T22	4567
transitions[0x1=>0x0]	337933	1		T5	3236		T6	6400		T22	4567

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	397921	1		T1	2		T2	1		T3	2
all_pins[0]	values[0x1]	147	1		T245	4		T246	1		T306	2
all_pins[0]	transitions[0x0=>0x1]	68	1		T245	3		T306	2		T307	1
all_pins[0]	transitions[0x1=>0x0]	72	1		T245	1		T246	2		T306	5
all_pins[1]	values[0x0]	397917	1		T1	2		T2	1		T3	2
all_pins[1]	values[0x1]	151	1		T245	2		T246	3		T306	5
all_pins[1]	transitions[0x0=>0x1]	121	1		T245	2		T246	3		T306	5
all_pins[1]	transitions[0x1=>0x0]	205	1		T324	55		T353	122		T245	1
all_pins[2]	values[0x0]	397833	1		T1	2		T2	1		T3	2
all_pins[2]	values[0x1]	235	1		T324	55		T353	122		T245	1
all_pins[2]	transitions[0x0=>0x1]	38	1		T245	1		T306	1		T307	3
all_pins[2]	transitions[0x1=>0x0]	253000	1		T5	1618		T6	6400		T22	2920
all_pins[3]	values[0x0]	144871	1		T1	2		T2	1		T3	2
all_pins[3]	values[0x1]	253197	1		T5	1618		T6	6400		T22	2920
all_pins[3]	transitions[0x0=>0x1]	221753	1		T5	1618		T6	4800		T22	2920
all_pins[3]	transitions[0x1=>0x0]	84516	1		T5	1618		T22	1647		T31	64
all_pins[4]	values[0x0]	282108	1		T1	2		T2	1		T3	2
all_pins[4]	values[0x1]	115960	1		T5	1618		T6	1600		T22	1647
all_pins[4]	transitions[0x0=>0x1]	115940	1		T5	1618		T6	1600		T22	1647
all_pins[4]	transitions[0x1=>0x0]	49	1		T246	1		T306	3		T307	1
all_pins[5]	values[0x0]	397999	1		T1	2		T2	1		T3	2
all_pins[5]	values[0x1]	69	1		T246	1		T306	3		T307	3
all_pins[5]	transitions[0x0=>0x1]	22	1		T307	2		T312	1		T354	1
all_pins[5]	transitions[0x1=>0x0]	91	1		T245	3		T307	3		T310	2