| T1069 |
/workspace/coverage/default/68.flash_ctrl_connect.1393990747 |
|
|
Jul 17 05:11:58 PM PDT 24 |
Jul 17 05:12:15 PM PDT 24 |
43158200 ps |
| T1070 |
/workspace/coverage/default/0.flash_ctrl_rd_buff_evict.656977599 |
|
|
Jul 17 05:05:38 PM PDT 24 |
Jul 17 05:07:56 PM PDT 24 |
5512948600 ps |
| T1071 |
/workspace/coverage/default/29.flash_ctrl_rw_evict.2838872330 |
|
|
Jul 17 05:10:29 PM PDT 24 |
Jul 17 05:10:59 PM PDT 24 |
45723300 ps |
| T1072 |
/workspace/coverage/default/46.flash_ctrl_alert_test.3415129798 |
|
|
Jul 17 05:12:49 PM PDT 24 |
Jul 17 05:13:04 PM PDT 24 |
59267000 ps |
| T1073 |
/workspace/coverage/default/9.flash_ctrl_ro_derr.598338518 |
|
|
Jul 17 05:07:49 PM PDT 24 |
Jul 17 05:10:07 PM PDT 24 |
1134345200 ps |
| T1074 |
/workspace/coverage/default/5.flash_ctrl_prog_reset.2922829214 |
|
|
Jul 17 05:06:52 PM PDT 24 |
Jul 17 05:07:08 PM PDT 24 |
37076300 ps |
| T1075 |
/workspace/coverage/default/20.flash_ctrl_sec_info_access.2039577139 |
|
|
Jul 17 05:09:39 PM PDT 24 |
Jul 17 05:10:47 PM PDT 24 |
4804014900 ps |
| T1076 |
/workspace/coverage/default/15.flash_ctrl_connect.1300220098 |
|
|
Jul 17 05:08:52 PM PDT 24 |
Jul 17 05:09:09 PM PDT 24 |
13495100 ps |
| T1077 |
/workspace/coverage/default/14.flash_ctrl_disable.1540685127 |
|
|
Jul 17 05:08:40 PM PDT 24 |
Jul 17 05:09:02 PM PDT 24 |
18306600 ps |
| T1078 |
/workspace/coverage/default/12.flash_ctrl_rw.523895037 |
|
|
Jul 17 05:08:16 PM PDT 24 |
Jul 17 05:17:55 PM PDT 24 |
6217740100 ps |
| T1079 |
/workspace/coverage/default/1.flash_ctrl_config_regwen.521063292 |
|
|
Jul 17 05:05:57 PM PDT 24 |
Jul 17 05:06:12 PM PDT 24 |
75091400 ps |
| T1080 |
/workspace/coverage/default/12.flash_ctrl_smoke.1967625668 |
|
|
Jul 17 05:08:13 PM PDT 24 |
Jul 17 05:11:06 PM PDT 24 |
75317600 ps |
| T1081 |
/workspace/coverage/default/14.flash_ctrl_rand_ops.1327078103 |
|
|
Jul 17 05:08:38 PM PDT 24 |
Jul 17 05:24:25 PM PDT 24 |
6006607100 ps |
| T1082 |
/workspace/coverage/default/1.flash_ctrl_host_addr_infection.3090810012 |
|
|
Jul 17 05:05:57 PM PDT 24 |
Jul 17 05:06:28 PM PDT 24 |
170323500 ps |
| T1083 |
/workspace/coverage/default/8.flash_ctrl_wo.477768039 |
|
|
Jul 17 05:07:25 PM PDT 24 |
Jul 17 05:10:09 PM PDT 24 |
3781694200 ps |
| T1084 |
/workspace/coverage/default/55.flash_ctrl_otp_reset.500640797 |
|
|
Jul 17 05:11:48 PM PDT 24 |
Jul 17 05:14:01 PM PDT 24 |
144373000 ps |
| T1085 |
/workspace/coverage/default/14.flash_ctrl_smoke.55274283 |
|
|
Jul 17 05:08:40 PM PDT 24 |
Jul 17 05:12:17 PM PDT 24 |
105226200 ps |
| T1086 |
/workspace/coverage/default/16.flash_ctrl_ro.1293213780 |
|
|
Jul 17 05:09:05 PM PDT 24 |
Jul 17 05:11:32 PM PDT 24 |
3996859600 ps |
| T1087 |
/workspace/coverage/default/61.flash_ctrl_otp_reset.1113756770 |
|
|
Jul 17 05:11:47 PM PDT 24 |
Jul 17 05:13:37 PM PDT 24 |
141736500 ps |
| T1088 |
/workspace/coverage/default/41.flash_ctrl_hw_sec_otp.849543833 |
|
|
Jul 17 05:14:43 PM PDT 24 |
Jul 17 05:16:06 PM PDT 24 |
2968588100 ps |
| T1089 |
/workspace/coverage/default/7.flash_ctrl_smoke.394303705 |
|
|
Jul 17 05:07:13 PM PDT 24 |
Jul 17 05:08:30 PM PDT 24 |
35520900 ps |
| T1090 |
/workspace/coverage/default/4.flash_ctrl_stress_all.3696464359 |
|
|
Jul 17 05:06:44 PM PDT 24 |
Jul 17 05:19:22 PM PDT 24 |
787357400 ps |
| T1091 |
/workspace/coverage/default/8.flash_ctrl_fetch_code.4169520902 |
|
|
Jul 17 05:07:26 PM PDT 24 |
Jul 17 05:07:54 PM PDT 24 |
292722600 ps |
| T1092 |
/workspace/coverage/default/12.flash_ctrl_hw_read_seed_err.1010543613 |
|
|
Jul 17 05:08:27 PM PDT 24 |
Jul 17 05:08:42 PM PDT 24 |
56587100 ps |
| T1093 |
/workspace/coverage/default/16.flash_ctrl_disable.2693673877 |
|
|
Jul 17 05:09:04 PM PDT 24 |
Jul 17 05:09:27 PM PDT 24 |
12411700 ps |
| T1094 |
/workspace/coverage/default/36.flash_ctrl_alert_test.1926470314 |
|
|
Jul 17 05:12:03 PM PDT 24 |
Jul 17 05:12:18 PM PDT 24 |
83233600 ps |
| T1095 |
/workspace/coverage/default/20.flash_ctrl_intr_rd_slow_flash.3013922017 |
|
|
Jul 17 05:09:43 PM PDT 24 |
Jul 17 05:11:57 PM PDT 24 |
64985323000 ps |
| T1096 |
/workspace/coverage/default/25.flash_ctrl_connect.3886675472 |
|
|
Jul 17 05:10:06 PM PDT 24 |
Jul 17 05:10:24 PM PDT 24 |
15327100 ps |
| T1097 |
/workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.3895788139 |
|
|
Jul 17 05:08:53 PM PDT 24 |
Jul 17 05:09:08 PM PDT 24 |
20540200 ps |
| T1098 |
/workspace/coverage/default/30.flash_ctrl_alert_test.3443329833 |
|
|
Jul 17 05:10:36 PM PDT 24 |
Jul 17 05:10:50 PM PDT 24 |
60353000 ps |
| T1099 |
/workspace/coverage/default/52.flash_ctrl_connect.1960910631 |
|
|
Jul 17 05:11:59 PM PDT 24 |
Jul 17 05:12:14 PM PDT 24 |
22483400 ps |
| T1100 |
/workspace/coverage/default/29.flash_ctrl_sec_info_access.649635932 |
|
|
Jul 17 05:10:33 PM PDT 24 |
Jul 17 05:11:28 PM PDT 24 |
4079014500 ps |
| T1101 |
/workspace/coverage/default/0.flash_ctrl_error_prog_type.55881017 |
|
|
Jul 17 05:05:39 PM PDT 24 |
Jul 17 05:51:08 PM PDT 24 |
518563000 ps |
| T1102 |
/workspace/coverage/default/19.flash_ctrl_hw_sec_otp.3751575046 |
|
|
Jul 17 05:09:25 PM PDT 24 |
Jul 17 05:10:33 PM PDT 24 |
2896542400 ps |
| T1103 |
/workspace/coverage/default/4.flash_ctrl_otp_reset.712006962 |
|
|
Jul 17 05:06:25 PM PDT 24 |
Jul 17 05:08:40 PM PDT 24 |
71762400 ps |
| T1104 |
/workspace/coverage/default/19.flash_ctrl_alert_test.4212807114 |
|
|
Jul 17 05:09:28 PM PDT 24 |
Jul 17 05:09:44 PM PDT 24 |
173200500 ps |
| T1105 |
/workspace/coverage/default/17.flash_ctrl_smoke.4002096210 |
|
|
Jul 17 05:09:04 PM PDT 24 |
Jul 17 05:11:35 PM PDT 24 |
701213300 ps |
| T1106 |
/workspace/coverage/default/23.flash_ctrl_connect.3266610009 |
|
|
Jul 17 05:09:51 PM PDT 24 |
Jul 17 05:10:08 PM PDT 24 |
15750900 ps |
| T1107 |
/workspace/coverage/default/1.flash_ctrl_sw_op.2659204847 |
|
|
Jul 17 05:05:54 PM PDT 24 |
Jul 17 05:06:21 PM PDT 24 |
296726700 ps |
| T1108 |
/workspace/coverage/default/32.flash_ctrl_otp_reset.2855065557 |
|
|
Jul 17 05:10:49 PM PDT 24 |
Jul 17 05:13:00 PM PDT 24 |
38496600 ps |
| T1109 |
/workspace/coverage/default/17.flash_ctrl_rw_evict.3024237003 |
|
|
Jul 17 05:09:16 PM PDT 24 |
Jul 17 05:09:48 PM PDT 24 |
128000100 ps |
| T1110 |
/workspace/coverage/default/3.flash_ctrl_intr_rd_slow_flash.666336232 |
|
|
Jul 17 05:06:26 PM PDT 24 |
Jul 17 05:11:44 PM PDT 24 |
47422234600 ps |
| T1111 |
/workspace/coverage/default/2.flash_ctrl_mp_regions.417488886 |
|
|
Jul 17 05:06:10 PM PDT 24 |
Jul 17 05:11:17 PM PDT 24 |
64155141300 ps |
| T1112 |
/workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.2994141417 |
|
|
Jul 17 05:07:02 PM PDT 24 |
Jul 17 05:07:34 PM PDT 24 |
70439300 ps |
| T1113 |
/workspace/coverage/default/16.flash_ctrl_rw_evict.1409995946 |
|
|
Jul 17 05:09:05 PM PDT 24 |
Jul 17 05:09:38 PM PDT 24 |
33681600 ps |
| T1114 |
/workspace/coverage/default/9.flash_ctrl_smoke.3321806918 |
|
|
Jul 17 05:07:38 PM PDT 24 |
Jul 17 05:11:19 PM PDT 24 |
82425200 ps |
| T1115 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2876637915 |
|
|
Jul 17 04:40:39 PM PDT 24 |
Jul 17 04:40:56 PM PDT 24 |
37465200 ps |
| T245 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3154904282 |
|
|
Jul 17 04:41:31 PM PDT 24 |
Jul 17 04:41:46 PM PDT 24 |
49994600 ps |
| T246 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.4173125770 |
|
|
Jul 17 04:41:28 PM PDT 24 |
Jul 17 04:41:42 PM PDT 24 |
41522300 ps |
| T73 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1252587973 |
|
|
Jul 17 04:40:59 PM PDT 24 |
Jul 17 04:41:54 PM PDT 24 |
2688684400 ps |
| T1116 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3490596818 |
|
|
Jul 17 04:39:18 PM PDT 24 |
Jul 17 04:39:45 PM PDT 24 |
26756800 ps |
| T1117 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.509120973 |
|
|
Jul 17 04:40:59 PM PDT 24 |
Jul 17 04:41:18 PM PDT 24 |
12468800 ps |
| T74 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2381603606 |
|
|
Jul 17 04:39:20 PM PDT 24 |
Jul 17 04:40:05 PM PDT 24 |
607682800 ps |
| T75 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1941230453 |
|
|
Jul 17 04:39:23 PM PDT 24 |
Jul 17 04:40:08 PM PDT 24 |
32909100 ps |
| T119 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.4041300204 |
|
|
Jul 17 04:39:18 PM PDT 24 |
Jul 17 04:40:19 PM PDT 24 |
111900100 ps |
| T306 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1483998608 |
|
|
Jul 17 04:41:14 PM PDT 24 |
Jul 17 04:41:29 PM PDT 24 |
17025500 ps |
| T120 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.909734570 |
|
|
Jul 17 04:39:44 PM PDT 24 |
Jul 17 04:40:03 PM PDT 24 |
49123200 ps |
| T121 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2963982167 |
|
|
Jul 17 04:40:43 PM PDT 24 |
Jul 17 04:47:10 PM PDT 24 |
1795513900 ps |
| T307 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.2868948976 |
|
|
Jul 17 04:40:12 PM PDT 24 |
Jul 17 04:40:28 PM PDT 24 |
28828700 ps |
| T1118 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1545096431 |
|
|
Jul 17 04:40:41 PM PDT 24 |
Jul 17 04:40:55 PM PDT 24 |
24600100 ps |
| T1119 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.1647454908 |
|
|
Jul 17 04:40:42 PM PDT 24 |
Jul 17 04:40:59 PM PDT 24 |
74480600 ps |
| T310 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.1038608360 |
|
|
Jul 17 04:41:28 PM PDT 24 |
Jul 17 04:41:43 PM PDT 24 |
60375200 ps |
| T122 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2394275533 |
|
|
Jul 17 04:40:42 PM PDT 24 |
Jul 17 04:48:24 PM PDT 24 |
1649175100 ps |
| T184 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1833655244 |
|
|
Jul 17 04:40:41 PM PDT 24 |
Jul 17 04:40:59 PM PDT 24 |
32263700 ps |
| T1120 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2363768473 |
|
|
Jul 17 04:40:57 PM PDT 24 |
Jul 17 04:41:13 PM PDT 24 |
43428600 ps |
| T221 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1889203160 |
|
|
Jul 17 04:40:29 PM PDT 24 |
Jul 17 04:53:12 PM PDT 24 |
2775823800 ps |
| T186 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1519756860 |
|
|
Jul 17 04:40:28 PM PDT 24 |
Jul 17 04:48:11 PM PDT 24 |
457144400 ps |
| T185 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1167773661 |
|
|
Jul 17 04:40:29 PM PDT 24 |
Jul 17 04:40:50 PM PDT 24 |
54761000 ps |
| T1121 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3548138952 |
|
|
Jul 17 04:39:58 PM PDT 24 |
Jul 17 04:40:15 PM PDT 24 |
38230400 ps |
| T216 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2163011030 |
|
|
Jul 17 04:40:42 PM PDT 24 |
Jul 17 04:53:18 PM PDT 24 |
347111000 ps |
| T1122 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.757449521 |
|
|
Jul 17 04:40:43 PM PDT 24 |
Jul 17 04:40:58 PM PDT 24 |
15595200 ps |
| T1123 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2352249378 |
|
|
Jul 17 04:40:57 PM PDT 24 |
Jul 17 04:41:13 PM PDT 24 |
31849200 ps |
| T283 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3880803478 |
|
|
Jul 17 04:39:20 PM PDT 24 |
Jul 17 04:39:56 PM PDT 24 |
205978300 ps |
| T311 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.1359608900 |
|
|
Jul 17 04:41:32 PM PDT 24 |
Jul 17 04:41:46 PM PDT 24 |
52489700 ps |
| T217 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2385909626 |
|
|
Jul 17 04:40:12 PM PDT 24 |
Jul 17 04:40:29 PM PDT 24 |
401777900 ps |
| T284 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3041787926 |
|
|
Jul 17 04:39:23 PM PDT 24 |
Jul 17 04:39:54 PM PDT 24 |
73195800 ps |
| T227 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1318895696 |
|
|
Jul 17 04:39:21 PM PDT 24 |
Jul 17 04:39:49 PM PDT 24 |
18649900 ps |
| T285 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1202246100 |
|
|
Jul 17 04:40:28 PM PDT 24 |
Jul 17 04:40:52 PM PDT 24 |
217813700 ps |
| T287 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3124597368 |
|
|
Jul 17 04:40:43 PM PDT 24 |
Jul 17 04:40:59 PM PDT 24 |
370027100 ps |
| T1124 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.4227415930 |
|
|
Jul 17 04:39:48 PM PDT 24 |
Jul 17 04:40:02 PM PDT 24 |
11402000 ps |
| T1125 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2223179519 |
|
|
Jul 17 04:39:32 PM PDT 24 |
Jul 17 04:40:26 PM PDT 24 |
24735300 ps |
| T1126 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2849700688 |
|
|
Jul 17 04:39:46 PM PDT 24 |
Jul 17 04:40:03 PM PDT 24 |
14843200 ps |
| T222 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2910971516 |
|
|
Jul 17 04:40:11 PM PDT 24 |
Jul 17 04:48:03 PM PDT 24 |
660795400 ps |
| T218 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.4235997983 |
|
|
Jul 17 04:40:58 PM PDT 24 |
Jul 17 04:41:18 PM PDT 24 |
77358200 ps |
| T312 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3807312079 |
|
|
Jul 17 04:40:11 PM PDT 24 |
Jul 17 04:40:25 PM PDT 24 |
31595000 ps |
| T219 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.660210217 |
|
|
Jul 17 04:39:29 PM PDT 24 |
Jul 17 04:40:00 PM PDT 24 |
155035000 ps |
| T308 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.907429348 |
|
|
Jul 17 04:39:18 PM PDT 24 |
Jul 17 04:39:44 PM PDT 24 |
17697500 ps |
| T309 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.868961196 |
|
|
Jul 17 04:41:30 PM PDT 24 |
Jul 17 04:41:45 PM PDT 24 |
16921100 ps |
| T354 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3780750636 |
|
|
Jul 17 04:41:15 PM PDT 24 |
Jul 17 04:41:30 PM PDT 24 |
68509000 ps |
| T1127 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.735435 |
|
|
Jul 17 04:40:27 PM PDT 24 |
Jul 17 04:40:41 PM PDT 24 |
51296500 ps |
| T220 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3605792910 |
|
|
Jul 17 04:40:59 PM PDT 24 |
Jul 17 04:41:17 PM PDT 24 |
134153300 ps |
| T1128 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2915829778 |
|
|
Jul 17 04:40:40 PM PDT 24 |
Jul 17 04:40:57 PM PDT 24 |
39155300 ps |
| T1129 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.1836403150 |
|
|
Jul 17 04:40:59 PM PDT 24 |
Jul 17 04:41:14 PM PDT 24 |
85014100 ps |
| T223 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2254785948 |
|
|
Jul 17 04:40:40 PM PDT 24 |
Jul 17 04:41:00 PM PDT 24 |
63367700 ps |
| T1130 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2004308584 |
|
|
Jul 17 04:40:31 PM PDT 24 |
Jul 17 04:40:48 PM PDT 24 |
133947300 ps |
| T286 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2154170948 |
|
|
Jul 17 04:40:44 PM PDT 24 |
Jul 17 04:41:03 PM PDT 24 |
350594600 ps |
| T1131 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.293446076 |
|
|
Jul 17 04:40:57 PM PDT 24 |
Jul 17 04:41:12 PM PDT 24 |
12948800 ps |
| T1132 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2201914122 |
|
|
Jul 17 04:39:33 PM PDT 24 |
Jul 17 04:39:55 PM PDT 24 |
14678300 ps |
| T250 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3315935047 |
|
|
Jul 17 04:40:59 PM PDT 24 |
Jul 17 04:56:20 PM PDT 24 |
3014984800 ps |
| T224 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1981919737 |
|
|
Jul 17 04:40:30 PM PDT 24 |
Jul 17 04:40:50 PM PDT 24 |
52254400 ps |
| T1133 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3302359014 |
|
|
Jul 17 04:39:44 PM PDT 24 |
Jul 17 04:39:59 PM PDT 24 |
103113100 ps |
| T1134 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1261677103 |
|
|
Jul 17 04:41:15 PM PDT 24 |
Jul 17 04:41:31 PM PDT 24 |
44252600 ps |
| T1135 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.37713116 |
|
|
Jul 17 04:39:58 PM PDT 24 |
Jul 17 04:40:12 PM PDT 24 |
56792000 ps |
| T1136 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.67305587 |
|
|
Jul 17 04:41:14 PM PDT 24 |
Jul 17 04:41:29 PM PDT 24 |
46177400 ps |
| T1137 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3829100698 |
|
|
Jul 17 04:40:41 PM PDT 24 |
Jul 17 04:40:58 PM PDT 24 |
13604700 ps |
| T1138 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.583435757 |
|
|
Jul 17 04:39:23 PM PDT 24 |
Jul 17 04:40:16 PM PDT 24 |
653645600 ps |
| T1139 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3849147235 |
|
|
Jul 17 04:40:13 PM PDT 24 |
Jul 17 04:40:31 PM PDT 24 |
43379300 ps |
| T1140 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.359984691 |
|
|
Jul 17 04:41:29 PM PDT 24 |
Jul 17 04:41:45 PM PDT 24 |
17801700 ps |
| T1141 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3249333532 |
|
|
Jul 17 04:40:59 PM PDT 24 |
Jul 17 04:41:17 PM PDT 24 |
135117400 ps |
| T244 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.797381363 |
|
|
Jul 17 04:40:31 PM PDT 24 |
Jul 17 04:40:49 PM PDT 24 |
32359200 ps |
| T1142 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2527816696 |
|
|
Jul 17 04:39:17 PM PDT 24 |
Jul 17 04:39:41 PM PDT 24 |
15485000 ps |
| T242 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3233197609 |
|
|
Jul 17 04:39:22 PM PDT 24 |
Jul 17 04:39:54 PM PDT 24 |
57605200 ps |
| T1143 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2033774208 |
|
|
Jul 17 04:40:39 PM PDT 24 |
Jul 17 04:40:53 PM PDT 24 |
17637300 ps |
| T1144 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2156341890 |
|
|
Jul 17 04:39:18 PM PDT 24 |
Jul 17 04:39:46 PM PDT 24 |
12003600 ps |
| T1145 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.954417356 |
|
|
Jul 17 04:40:30 PM PDT 24 |
Jul 17 04:40:47 PM PDT 24 |
122621200 ps |
| T1146 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3977173953 |
|
|
Jul 17 04:39:21 PM PDT 24 |
Jul 17 04:39:52 PM PDT 24 |
50864600 ps |
| T288 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.736055008 |
|
|
Jul 17 04:40:57 PM PDT 24 |
Jul 17 04:41:16 PM PDT 24 |
118656800 ps |
| T243 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2482772197 |
|
|
Jul 17 04:39:23 PM PDT 24 |
Jul 17 04:39:57 PM PDT 24 |
435094800 ps |
| T1147 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3709668591 |
|
|
Jul 17 04:40:12 PM PDT 24 |
Jul 17 04:40:29 PM PDT 24 |
15120000 ps |
| T305 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.4041182276 |
|
|
Jul 17 04:39:31 PM PDT 24 |
Jul 17 04:39:57 PM PDT 24 |
161273700 ps |
| T248 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2128669402 |
|
|
Jul 17 04:39:30 PM PDT 24 |
Jul 17 04:39:59 PM PDT 24 |
97918100 ps |
| T1148 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.493257312 |
|
|
Jul 17 04:40:57 PM PDT 24 |
Jul 17 04:41:17 PM PDT 24 |
85063800 ps |
| T1149 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.4039105562 |
|
|
Jul 17 04:41:15 PM PDT 24 |
Jul 17 04:41:30 PM PDT 24 |
30635100 ps |
| T251 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3072974048 |
|
|
Jul 17 04:41:17 PM PDT 24 |
Jul 17 04:41:36 PM PDT 24 |
634954100 ps |
| T1150 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.787602071 |
|
|
Jul 17 04:40:40 PM PDT 24 |
Jul 17 04:40:57 PM PDT 24 |
34083700 ps |
| T1151 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.4135649799 |
|
|
Jul 17 04:40:29 PM PDT 24 |
Jul 17 04:40:49 PM PDT 24 |
122784200 ps |
| T1152 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1407901758 |
|
|
Jul 17 04:40:29 PM PDT 24 |
Jul 17 04:40:47 PM PDT 24 |
12906300 ps |
| T1153 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1374942604 |
|
|
Jul 17 04:41:14 PM PDT 24 |
Jul 17 04:41:45 PM PDT 24 |
124251300 ps |
| T256 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1601788267 |
|
|
Jul 17 04:40:11 PM PDT 24 |
Jul 17 04:40:32 PM PDT 24 |
80625100 ps |
| T1154 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3510701485 |
|
|
Jul 17 04:39:41 PM PDT 24 |
Jul 17 04:40:37 PM PDT 24 |
1565570500 ps |
| T1155 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.636404988 |
|
|
Jul 17 04:40:44 PM PDT 24 |
Jul 17 04:41:04 PM PDT 24 |
476099800 ps |
| T1156 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.611619087 |
|
|
Jul 17 04:40:13 PM PDT 24 |
Jul 17 04:40:31 PM PDT 24 |
158390000 ps |
| T1157 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1940024675 |
|
|
Jul 17 04:40:28 PM PDT 24 |
Jul 17 04:40:46 PM PDT 24 |
13255000 ps |
| T1158 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2175439614 |
|
|
Jul 17 04:39:24 PM PDT 24 |
Jul 17 04:39:52 PM PDT 24 |
44587800 ps |
| T1159 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.3871823434 |
|
|
Jul 17 04:41:28 PM PDT 24 |
Jul 17 04:41:44 PM PDT 24 |
64446600 ps |
| T1160 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.609872053 |
|
|
Jul 17 04:40:44 PM PDT 24 |
Jul 17 04:40:59 PM PDT 24 |
11761900 ps |
| T247 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1326961153 |
|
|
Jul 17 04:40:40 PM PDT 24 |
Jul 17 04:41:02 PM PDT 24 |
432478400 ps |
| T357 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.3640325858 |
|
|
Jul 17 04:39:22 PM PDT 24 |
Jul 17 04:52:20 PM PDT 24 |
4720943700 ps |
| T1161 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3106883544 |
|
|
Jul 17 04:40:28 PM PDT 24 |
Jul 17 04:40:46 PM PDT 24 |
34084900 ps |
| T1162 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3706724883 |
|
|
Jul 17 04:40:43 PM PDT 24 |
Jul 17 04:41:35 PM PDT 24 |
1751656400 ps |
| T1163 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1278625061 |
|
|
Jul 17 04:39:30 PM PDT 24 |
Jul 17 04:39:59 PM PDT 24 |
84114800 ps |
| T1164 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2083103540 |
|
|
Jul 17 04:40:41 PM PDT 24 |
Jul 17 04:40:56 PM PDT 24 |
44839500 ps |
| T1165 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.423056562 |
|
|
Jul 17 04:39:18 PM PDT 24 |
Jul 17 04:39:45 PM PDT 24 |
31407300 ps |
| T1166 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3062705807 |
|
|
Jul 17 04:40:11 PM PDT 24 |
Jul 17 04:40:29 PM PDT 24 |
121177300 ps |
| T1167 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2621847036 |
|
|
Jul 17 04:39:24 PM PDT 24 |
Jul 17 04:40:23 PM PDT 24 |
101513900 ps |
| T1168 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.163434907 |
|
|
Jul 17 04:40:57 PM PDT 24 |
Jul 17 04:41:17 PM PDT 24 |
127780700 ps |
| T1169 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1242294944 |
|
|
Jul 17 04:39:44 PM PDT 24 |
Jul 17 04:40:20 PM PDT 24 |
83852600 ps |
| T1170 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2142635309 |
|
|
Jul 17 04:39:30 PM PDT 24 |
Jul 17 04:39:53 PM PDT 24 |
129324200 ps |
| T1171 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1571268113 |
|
|
Jul 17 04:40:39 PM PDT 24 |
Jul 17 04:40:57 PM PDT 24 |
14812900 ps |
| T254 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1906083899 |
|
|
Jul 17 04:39:44 PM PDT 24 |
Jul 17 04:47:32 PM PDT 24 |
2219354100 ps |
| T1172 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2796728933 |
|
|
Jul 17 04:40:58 PM PDT 24 |
Jul 17 04:41:16 PM PDT 24 |
68282400 ps |
| T1173 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1470402200 |
|
|
Jul 17 04:41:14 PM PDT 24 |
Jul 17 04:41:30 PM PDT 24 |
28257400 ps |
| T1174 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2082778699 |
|
|
Jul 17 04:40:43 PM PDT 24 |
Jul 17 04:41:19 PM PDT 24 |
850167900 ps |
| T1175 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2346251029 |
|
|
Jul 17 04:40:42 PM PDT 24 |
Jul 17 04:40:58 PM PDT 24 |
69897300 ps |
| T1176 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.887592668 |
|
|
Jul 17 04:41:15 PM PDT 24 |
Jul 17 04:41:30 PM PDT 24 |
16359100 ps |
| T1177 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3373060835 |
|
|
Jul 17 04:40:14 PM PDT 24 |
Jul 17 04:40:31 PM PDT 24 |
27432800 ps |
| T1178 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3339089796 |
|
|
Jul 17 04:39:31 PM PDT 24 |
Jul 17 04:39:56 PM PDT 24 |
12447500 ps |
| T1179 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.589945659 |
|
|
Jul 17 04:41:29 PM PDT 24 |
Jul 17 04:41:45 PM PDT 24 |
15161600 ps |
| T1180 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.392732655 |
|
|
Jul 17 04:41:00 PM PDT 24 |
Jul 17 04:41:19 PM PDT 24 |
68686100 ps |
| T1181 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.743618439 |
|
|
Jul 17 04:40:40 PM PDT 24 |
Jul 17 04:41:16 PM PDT 24 |
305264400 ps |
| T1182 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.29517122 |
|
|
Jul 17 04:40:12 PM PDT 24 |
Jul 17 04:40:32 PM PDT 24 |
109741300 ps |
| T1183 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.239243064 |
|
|
Jul 17 04:39:29 PM PDT 24 |
Jul 17 04:39:56 PM PDT 24 |
440227800 ps |
| T252 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.468898434 |
|
|
Jul 17 04:40:30 PM PDT 24 |
Jul 17 04:40:52 PM PDT 24 |
432280500 ps |
| T228 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.50171395 |
|
|
Jul 17 04:39:23 PM PDT 24 |
Jul 17 04:39:50 PM PDT 24 |
37276200 ps |
| T255 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1347472027 |
|
|
Jul 17 04:40:43 PM PDT 24 |
Jul 17 04:53:08 PM PDT 24 |
1351086600 ps |
| T1184 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1851305680 |
|
|
Jul 17 04:40:27 PM PDT 24 |
Jul 17 04:40:42 PM PDT 24 |
18030200 ps |
| T1185 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.3621986387 |
|
|
Jul 17 04:40:42 PM PDT 24 |
Jul 17 04:40:58 PM PDT 24 |
18230800 ps |
| T356 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.4035745778 |
|
|
Jul 17 04:40:27 PM PDT 24 |
Jul 17 04:40:49 PM PDT 24 |
43925400 ps |
| T1186 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1494784501 |
|
|
Jul 17 04:40:43 PM PDT 24 |
Jul 17 04:41:30 PM PDT 24 |
831291600 ps |
| T229 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2229259313 |
|
|
Jul 17 04:39:19 PM PDT 24 |
Jul 17 04:39:46 PM PDT 24 |
30019900 ps |
| T1187 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3513997198 |
|
|
Jul 17 04:41:17 PM PDT 24 |
Jul 17 04:41:32 PM PDT 24 |
51727000 ps |
| T1188 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.214520000 |
|
|
Jul 17 04:39:31 PM PDT 24 |
Jul 17 04:39:56 PM PDT 24 |
17745300 ps |
| T1189 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1277014767 |
|
|
Jul 17 04:41:30 PM PDT 24 |
Jul 17 04:41:45 PM PDT 24 |
27765700 ps |
| T249 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.397205180 |
|
|
Jul 17 04:39:56 PM PDT 24 |
Jul 17 04:40:16 PM PDT 24 |
151990000 ps |
| T1190 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.739666232 |
|
|
Jul 17 04:40:44 PM PDT 24 |
Jul 17 04:41:03 PM PDT 24 |
410950100 ps |
| T1191 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3875669792 |
|
|
Jul 17 04:41:14 PM PDT 24 |
Jul 17 04:41:32 PM PDT 24 |
73267100 ps |
| T1192 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1327580590 |
|
|
Jul 17 04:39:43 PM PDT 24 |
Jul 17 04:39:58 PM PDT 24 |
14307100 ps |
| T1193 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1196487531 |
|
|
Jul 17 04:41:13 PM PDT 24 |
Jul 17 04:41:28 PM PDT 24 |
26922300 ps |
| T1194 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2172495942 |
|
|
Jul 17 04:40:12 PM PDT 24 |
Jul 17 04:40:29 PM PDT 24 |
165554500 ps |
| T1195 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1908861145 |
|
|
Jul 17 04:39:21 PM PDT 24 |
Jul 17 04:40:08 PM PDT 24 |
227948900 ps |
| T1196 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3067301269 |
|
|
Jul 17 04:41:13 PM PDT 24 |
Jul 17 04:41:28 PM PDT 24 |
16793600 ps |
| T1197 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.303104654 |
|
|
Jul 17 04:40:30 PM PDT 24 |
Jul 17 04:40:48 PM PDT 24 |
11423600 ps |
| T362 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3468494051 |
|
|
Jul 17 04:40:28 PM PDT 24 |
Jul 17 04:55:44 PM PDT 24 |
9610830100 ps |
| T1198 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.496591179 |
|
|
Jul 17 04:41:31 PM PDT 24 |
Jul 17 04:41:47 PM PDT 24 |
41870800 ps |
| T1199 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1637482645 |
|
|
Jul 17 04:40:12 PM PDT 24 |
Jul 17 04:40:31 PM PDT 24 |
96229700 ps |
| T1200 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3940604949 |
|
|
Jul 17 04:39:19 PM PDT 24 |
Jul 17 04:40:13 PM PDT 24 |
456780000 ps |
| T1201 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.3463891721 |
|
|
Jul 17 04:40:27 PM PDT 24 |
Jul 17 04:40:45 PM PDT 24 |
371551900 ps |
| T1202 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.655227326 |
|
|
Jul 17 04:40:44 PM PDT 24 |
Jul 17 04:40:59 PM PDT 24 |
27662100 ps |
| T360 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.518654390 |
|
|
Jul 17 04:40:41 PM PDT 24 |
Jul 17 04:48:22 PM PDT 24 |
896165500 ps |
| T253 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1484461302 |
|
|
Jul 17 04:40:41 PM PDT 24 |
Jul 17 04:41:03 PM PDT 24 |
112374900 ps |
| T1203 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.3165667095 |
|
|
Jul 17 04:40:30 PM PDT 24 |
Jul 17 04:40:45 PM PDT 24 |
22559300 ps |
| T1204 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.615433770 |
|
|
Jul 17 04:41:13 PM PDT 24 |
Jul 17 04:41:30 PM PDT 24 |
30029200 ps |
| T361 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.3819674340 |
|
|
Jul 17 04:39:23 PM PDT 24 |
Jul 17 04:46:02 PM PDT 24 |
800395600 ps |
| T1205 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3793669594 |
|
|
Jul 17 04:41:14 PM PDT 24 |
Jul 17 04:47:40 PM PDT 24 |
287865500 ps |
| T1206 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3161055803 |
|
|
Jul 17 04:40:14 PM PDT 24 |
Jul 17 04:40:36 PM PDT 24 |
63779300 ps |
| T1207 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3948604492 |
|
|
Jul 17 04:40:39 PM PDT 24 |
Jul 17 04:40:57 PM PDT 24 |
115562400 ps |
| T1208 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3321307063 |
|
|
Jul 17 04:40:28 PM PDT 24 |
Jul 17 04:40:45 PM PDT 24 |
150792100 ps |
| T358 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.520912644 |
|
|
Jul 17 04:39:57 PM PDT 24 |
Jul 17 04:52:37 PM PDT 24 |
661803500 ps |
| T1209 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2727408653 |
|
|
Jul 17 04:40:41 PM PDT 24 |
Jul 17 04:40:59 PM PDT 24 |
594062200 ps |
| T1210 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2209632688 |
|
|
Jul 17 04:40:57 PM PDT 24 |
Jul 17 04:41:14 PM PDT 24 |
239426800 ps |
| T1211 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2710831134 |
|
|
Jul 17 04:40:42 PM PDT 24 |
Jul 17 04:41:01 PM PDT 24 |
46809500 ps |
| T1212 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3870711144 |
|
|
Jul 17 04:41:31 PM PDT 24 |
Jul 17 04:41:46 PM PDT 24 |
31365000 ps |
| T1213 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1902232227 |
|
|
Jul 17 04:40:30 PM PDT 24 |
Jul 17 04:40:49 PM PDT 24 |
1252349900 ps |
| T1214 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.944118133 |
|
|
Jul 17 04:40:11 PM PDT 24 |
Jul 17 04:40:26 PM PDT 24 |
55269000 ps |
| T1215 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2650963391 |
|
|
Jul 17 04:40:59 PM PDT 24 |
Jul 17 04:41:21 PM PDT 24 |
87961900 ps |
| T1216 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2743959253 |
|
|
Jul 17 04:39:33 PM PDT 24 |
Jul 17 04:39:57 PM PDT 24 |
16655500 ps |
| T1217 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2325049073 |
|
|
Jul 17 04:40:29 PM PDT 24 |
Jul 17 04:40:48 PM PDT 24 |
26936800 ps |
| T257 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.2959725808 |
|
|
Jul 17 04:40:12 PM PDT 24 |
Jul 17 04:40:34 PM PDT 24 |
59966000 ps |
| T1218 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.439807829 |
|
|
Jul 17 04:41:14 PM PDT 24 |
Jul 17 04:41:28 PM PDT 24 |
15713800 ps |
| T1219 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2186326031 |
|
|
Jul 17 04:41:14 PM PDT 24 |
Jul 17 04:41:29 PM PDT 24 |
16790400 ps |
| T230 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3605289278 |
|
|
Jul 17 04:40:59 PM PDT 24 |
Jul 17 04:41:15 PM PDT 24 |
18386700 ps |
| T1220 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.585260757 |
|
|
Jul 17 04:41:16 PM PDT 24 |
Jul 17 04:41:31 PM PDT 24 |
29814100 ps |
| T1221 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2055044850 |
|
|
Jul 17 04:40:11 PM PDT 24 |
Jul 17 04:40:28 PM PDT 24 |
66249400 ps |
| T359 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1030402403 |
|
|
Jul 17 04:39:16 PM PDT 24 |
Jul 17 04:45:52 PM PDT 24 |
3373247800 ps |
| T1222 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.4161115413 |
|
|
Jul 17 04:40:11 PM PDT 24 |
Jul 17 04:40:29 PM PDT 24 |
68447200 ps |
| T1223 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1685807790 |
|
|
Jul 17 04:40:30 PM PDT 24 |
Jul 17 04:41:05 PM PDT 24 |
96229200 ps |
| T1224 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.411378023 |
|
|
Jul 17 04:39:21 PM PDT 24 |
Jul 17 04:40:40 PM PDT 24 |
2530523300 ps |
| T1225 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2140777169 |
|
|
Jul 17 04:39:45 PM PDT 24 |
Jul 17 04:40:00 PM PDT 24 |
23834500 ps |
| T1226 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3962285742 |
|
|
Jul 17 04:39:32 PM PDT 24 |
Jul 17 04:39:54 PM PDT 24 |
18735200 ps |
| T1227 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3701184079 |
|
|
Jul 17 04:40:43 PM PDT 24 |
Jul 17 04:41:01 PM PDT 24 |
61716300 ps |
| T1228 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3844070416 |
|
|
Jul 17 04:40:27 PM PDT 24 |
Jul 17 04:40:45 PM PDT 24 |
18888300 ps |
| T1229 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3046850234 |
|
|
Jul 17 04:40:13 PM PDT 24 |
Jul 17 04:40:31 PM PDT 24 |
14702600 ps |
| T1230 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.346929456 |
|
|
Jul 17 04:40:42 PM PDT 24 |
Jul 17 04:41:01 PM PDT 24 |
46310400 ps |
| T1231 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3725271771 |
|
|
Jul 17 04:41:15 PM PDT 24 |
Jul 17 04:41:33 PM PDT 24 |
16929200 ps |
| T1232 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.2823049889 |
|
|
Jul 17 04:41:17 PM PDT 24 |
Jul 17 04:41:32 PM PDT 24 |
19887200 ps |
| T364 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3572915050 |
|
|
Jul 17 04:40:57 PM PDT 24 |
Jul 17 04:47:21 PM PDT 24 |
863165900 ps |
| T1233 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.653367915 |
|
|
Jul 17 04:39:32 PM PDT 24 |
Jul 17 04:40:00 PM PDT 24 |
58588200 ps |
| T1234 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3538428911 |
|
|
Jul 17 04:40:29 PM PDT 24 |
Jul 17 04:40:48 PM PDT 24 |
38875700 ps |
| T1235 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2222671798 |
|
|
Jul 17 04:39:46 PM PDT 24 |
Jul 17 04:41:07 PM PDT 24 |
2280640600 ps |
| T1236 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.4066162351 |
|
|
Jul 17 04:40:30 PM PDT 24 |
Jul 17 04:40:46 PM PDT 24 |
66159300 ps |
| T363 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1901493432 |
|
|
Jul 17 04:40:10 PM PDT 24 |
Jul 17 04:55:18 PM PDT 24 |
1359790000 ps |
| T1237 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2384597376 |
|
|
Jul 17 04:41:31 PM PDT 24 |
Jul 17 04:41:46 PM PDT 24 |
28849500 ps |
| T289 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.272617210 |
|
|
Jul 17 04:40:12 PM PDT 24 |
Jul 17 04:40:45 PM PDT 24 |
786574700 ps |
| T1238 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2076827004 |
|
|
Jul 17 04:40:41 PM PDT 24 |
Jul 17 04:41:03 PM PDT 24 |
48632800 ps |
| T1239 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2937549393 |
|
|
Jul 17 04:40:59 PM PDT 24 |
Jul 17 04:56:13 PM PDT 24 |
693023200 ps |
| T1240 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2406750569 |
|
|
Jul 17 04:41:14 PM PDT 24 |
Jul 17 04:41:30 PM PDT 24 |
54836100 ps |
| T1241 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.3603255849 |
|
|
Jul 17 04:41:13 PM PDT 24 |
Jul 17 04:41:29 PM PDT 24 |
14725500 ps |
| T1242 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2092718021 |
|
|
Jul 17 04:40:12 PM PDT 24 |
Jul 17 04:40:29 PM PDT 24 |
15987500 ps |
| T1243 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1752559596 |
|
|
Jul 17 04:40:13 PM PDT 24 |
Jul 17 04:40:32 PM PDT 24 |
106248100 ps |
| T290 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2153160477 |
|
|
Jul 17 04:40:43 PM PDT 24 |
Jul 17 04:41:02 PM PDT 24 |
403055900 ps |
| T1244 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.853664684 |
|
|
Jul 17 04:40:57 PM PDT 24 |
Jul 17 04:41:16 PM PDT 24 |
71625300 ps |
| T1245 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.2510928762 |
|
|
Jul 17 04:41:14 PM PDT 24 |
Jul 17 04:41:30 PM PDT 24 |
44383100 ps |
| T1246 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.920997312 |
|
|
Jul 17 04:39:23 PM PDT 24 |
Jul 17 04:39:54 PM PDT 24 |
182544800 ps |
| T1247 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.2078644756 |
|
|
Jul 17 04:39:19 PM PDT 24 |
Jul 17 04:39:46 PM PDT 24 |
21932900 ps |
| T1248 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2758283568 |
|
|
Jul 17 04:39:44 PM PDT 24 |
Jul 17 04:40:32 PM PDT 24 |
158785400 ps |
| T1249 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.3653681690 |
|
|
Jul 17 04:41:28 PM PDT 24 |
Jul 17 04:41:43 PM PDT 24 |
16353600 ps |
| T1250 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2522932293 |
|
|
Jul 17 04:40:12 PM PDT 24 |
Jul 17 04:47:54 PM PDT 24 |
1398555700 ps |
| T1251 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3149679574 |
|
|
Jul 17 04:40:28 PM PDT 24 |
Jul 17 04:40:46 PM PDT 24 |
32014900 ps |
| T1252 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.996008378 |
|
|
Jul 17 04:41:30 PM PDT 24 |
Jul 17 04:41:46 PM PDT 24 |
42010700 ps |
| T1253 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2858848860 |
|
|
Jul 17 04:40:58 PM PDT 24 |
Jul 17 04:41:19 PM PDT 24 |
84208400 ps |