Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	307315	1		T1	3465		T2	2		T3	1
all_values[1]	307315	1		T1	3465		T2	2		T3	1
all_values[2]	307315	1		T1	3465		T2	2		T3	1
all_values[3]	307315	1		T1	3465		T2	2		T3	1
all_values[4]	307315	1		T1	3465		T2	2		T3	1
all_values[5]	307315	1		T1	3465		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	620866	1		T1	6934		T2	12		T3	6
auto[1]	1223024	1		T1	13856		T21	6392		T24	13376

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	902792	1		T1	10396		T2	7		T3	4
auto[1]	941098	1		T1	10394		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	307157	1		T1	3465		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	158	1		T283	4		T284	4		T362	5
all_values[1]	auto[0]	auto[1]	307166	1		T1	3465		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	149	1		T283	1		T284	3		T362	5
all_values[2]	auto[0]	auto[0]	1576	1		T1	1		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	62	1		T283	1		T284	3		T362	3
all_values[2]	auto[1]	auto[0]	305625	1		T1	3464		T21	1598		T24	3344
all_values[2]	auto[1]	auto[1]	52	1		T362	2		T364	1		T366	1
all_values[3]	auto[0]	auto[0]	1577	1		T1	1		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	60	1		T284	1		T362	1		T363	1
all_values[3]	auto[1]	auto[0]	78842	1		T1	1732		T21	1598		T24	1672
all_values[3]	auto[1]	auto[1]	226836	1		T1	1732		T24	1672		T34	4110
all_values[4]	auto[0]	auto[0]	1134	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	509	1		T2	1		T18	1		T7	1
all_values[4]	auto[1]	auto[0]	206880	1		T1	1732		T21	1		T24	1672
all_values[4]	auto[1]	auto[1]	98792	1		T1	1732		T21	1597		T24	1672
all_values[5]	auto[0]	auto[0]	1524	1		T1	1		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	101	1		T36	1		T37	1		T38	1
all_values[5]	auto[1]	auto[0]	305634	1		T1	3464		T21	1598		T24	3344
all_values[5]	auto[1]	auto[1]	56	1		T362	2		T363	1		T364	3