Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	246117	1		T1	879		T2	63		T18	402
auto[FlashEraseBank]	271907	1		T1	853		T2	34		T7	3

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	256896	1		T1	1732		T18	10		T7	3
auto[FlashOpProgram]	240969	1		T2	97		T18	384		T7	5
auto[FlashOpErase]	16159	1		T18	8		T7	1		T4	9
auto[FlashOpInvalid]	4000	1		T140	200		T141	200		T144	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	256896	1		T1	1732		T18	10		T7	3
op[FlashOpProgram]	240969	1		T2	97		T18	384		T7	5
op[FlashOpErase]	16159	1		T18	8		T7	1		T4	9
read_erase_read	593	1		T18	2		T7	1		T5	2
read_prog_read	816	1		T5	1		T26	1		T61	1

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	372739	1		T1	1732		T2	97		T7	9
auto[FlashPartInfo]	141817	1		T18	402		T4	371		T21	231
auto[FlashPartInfo1]	788	1		T60	64		T31	34		T195	2
auto[FlashPartInfo2]	2680	1		T21	7		T26	1		T60	128

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	182282	1		T1	1732		T7	3		T5	8
auto[FlashPartData]	auto[FlashOpProgram]	182951	1		T2	97		T7	5		T20	14
auto[FlashPartData]	auto[FlashOpErase]	3596	1		T7	1		T5	4		T41	6
auto[FlashPartData]	auto[FlashOpInvalid]	3910	1		T140	194		T141	194		T144	192
auto[FlashPartInfo]	auto[FlashOpRead]	72281	1		T18	10		T4	10		T25	4
auto[FlashPartInfo]	auto[FlashOpProgram]	56919	1		T18	384		T4	352		T21	231
auto[FlashPartInfo]	auto[FlashOpErase]	12533	1		T18	8		T4	9		T6	6
auto[FlashPartInfo]	auto[FlashOpInvalid]	84	1		T140	4		T141	6		T144	8
auto[FlashPartInfo1]	auto[FlashOpRead]	616	1		T60	32		T31	34		T195	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	165	1		T60	32		T127	32		T145	32
auto[FlashPartInfo1]	auto[FlashOpErase]	5	1		T437	1		T129	1		T132	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T129	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1717	1		T26	1		T60	64		T42	10
auto[FlashPartInfo2]	auto[FlashOpProgram]	934	1		T21	7		T60	64		T29	1
auto[FlashPartInfo2]	auto[FlashOpErase]	25	1		T140	1		T160	1		T162	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	4	1		T140	2		T162	2		-	-