Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.86	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	3	29	90.62

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	3	29	90.62	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31719	1		T4	4		T5	32		T56	124
auto[1]	25	1		T377	1		T378	4		T379	5
auto[2]	26	1		T196	4		T380	1		T378	1
auto[3]	240	1		T28	14		T92	1		T215	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8004	1		T4	1		T5	8		T56	31
evic_idx[1]	7994	1		T4	1		T5	8		T56	31
evic_idx[2]	8007	1		T4	1		T5	8		T56	31
evic_idx[3]	8005	1		T4	1		T5	8		T56	31

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31145	1		T4	4		T5	12		T56	124
evic_op[2]	301	1		T5	16		T41	1		T61	16

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	3	29	90.62	3

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[1]]	*	[auto[2]]	--	--	2

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	[evic_op[2]]	[auto[1]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7729	1		T4	1		T5	3		T56	31
evic_idx[0]	evic_op[1]	auto[1]	3	1		T378	1		T381	1		T382	1
evic_idx[0]	evic_op[1]	auto[2]	1	1		T383	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	53	1		T28	3		T247	1		T380	1
evic_idx[0]	evic_op[2]	auto[0]	63	1		T5	4		T61	4		T63	10
evic_idx[0]	evic_op[2]	auto[2]	1	1		T384	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	13	1		T92	1		T385	1		T210	1
evic_idx[1]	evic_op[1]	auto[0]	7729	1		T4	1		T5	3		T56	31
evic_idx[1]	evic_op[1]	auto[1]	6	1		T378	1		T379	1		T381	3
evic_idx[1]	evic_op[1]	auto[3]	46	1		T28	3		T247	1		T380	2
evic_idx[1]	evic_op[2]	auto[0]	62	1		T5	4		T61	4		T63	10
evic_idx[1]	evic_op[2]	auto[1]	2	1		T386	1		T387	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	8	1		T224	1		T214	1		T308	1
evic_idx[2]	evic_op[1]	auto[0]	7732	1		T4	1		T5	3		T56	31
evic_idx[2]	evic_op[1]	auto[1]	6	1		T378	1		T379	2		T381	2
evic_idx[2]	evic_op[1]	auto[2]	3	1		T378	1		T383	1		T382	1
evic_idx[2]	evic_op[1]	auto[3]	52	1		T28	4		T380	3		T388	4
evic_idx[2]	evic_op[2]	auto[0]	63	1		T5	4		T61	4		T63	10
evic_idx[2]	evic_op[2]	auto[1]	1	1		T389	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[2]	2	1		T384	1		T390	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	7	1		T223	1		T309	1		T346	1
evic_idx[3]	evic_op[1]	auto[0]	7729	1		T4	1		T5	3		T56	31
evic_idx[3]	evic_op[1]	auto[1]	4	1		T378	1		T379	2		T381	1
evic_idx[3]	evic_op[1]	auto[2]	1	1		T380	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	51	1		T28	4		T380	2		T388	4
evic_idx[3]	evic_op[2]	auto[0]	64	1		T5	4		T41	1		T61	4
evic_idx[3]	evic_op[2]	auto[1]	3	1		T377	1		T391	1		T392	1
evic_idx[3]	evic_op[2]	auto[2]	2	1		T393	1		T384	1		-	-
evic_idx[3]	evic_op[2]	auto[3]	10	1		T215	1		T216	1		T394	1