Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	23709	1		T239	14242		T368	1822		T369	2707
rd_lvl[2]	47761	1		T34	1544		T226	13574		T239	10174
rd_lvl[3]	13199	1		T34	810		T226	329		T370	393
rd_lvl[4]	30231	1		T34	112		T371	5728		T368	466
rd_lvl[5]	13556	1		T34	388		T371	1356		T368	210
rd_lvl[6]	11122	1		T34	431		T372	100		T373	2488
rd_lvl[7]	7761	1		T34	44		T372	35		T373	434
rd_lvl[8]	11631	1		T34	41		T374	727		T368	147
rd_lvl[9]	8673	1		T1	452		T34	41		T374	107
rd_lvl[10]	10667	1		T1	1280		T368	78		T369	999
rd_lvl[11]	5845	1		T24	463		T32	266		T374	130
rd_lvl[12]	11078	1		T24	1209		T34	4		T32	235
rd_lvl[13]	2991	1		T34	3		T368	2		T375	1186
rd_lvl[14]	3363	1		T32	116		T33	222		T376	67
rd_lvl[15]	2402	1		T31	164		T33	69		T335	279