Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	307315	1		T1	3465		T2	2		T3	1
all_pins[1]	307315	1		T1	3465		T2	2		T3	1
all_pins[2]	307315	1		T1	3465		T2	2		T3	1
all_pins[3]	307315	1		T1	3465		T2	2		T3	1
all_pins[4]	307315	1		T1	3465		T2	2		T3	1
all_pins[5]	307315	1		T1	3465		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1527807	1		T1	17326		T2	12		T3	6
values[0x1]	316083	1		T1	3464		T21	1597		T24	3344
transitions[0x0=>0x1]	285917	1		T1	3464		T21	1597		T24	3344
transitions[0x1=>0x0]	285903	1		T1	3464		T21	1597		T24	3344

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	307157	1		T1	3465		T2	2		T3	1
all_pins[0]	values[0x1]	158	1		T283	4		T284	4		T362	5
all_pins[0]	transitions[0x0=>0x1]	84	1		T283	3		T284	1		T362	1
all_pins[0]	transitions[0x1=>0x0]	75	1		T362	1		T363	1		T364	1
all_pins[1]	values[0x0]	307166	1		T1	3465		T2	2		T3	1
all_pins[1]	values[0x1]	149	1		T283	1		T284	3		T362	5
all_pins[1]	transitions[0x0=>0x1]	127	1		T283	1		T284	3		T362	4
all_pins[1]	transitions[0x1=>0x0]	2328	1		T31	68		T33	145		T335	280
all_pins[2]	values[0x0]	304965	1		T1	3465		T2	2		T3	1
all_pins[2]	values[0x1]	2350	1		T31	68		T33	145		T335	280
all_pins[2]	transitions[0x0=>0x1]	39	1		T362	2		T364	1		T395	2
all_pins[2]	transitions[0x1=>0x0]	204384	1		T1	1732		T24	1672		T34	3418
all_pins[3]	values[0x0]	100620	1		T1	1733		T2	2		T3	1
all_pins[3]	values[0x1]	206695	1		T1	1732		T24	1672		T34	3418
all_pins[3]	transitions[0x0=>0x1]	178994	1		T1	1732		T24	1672		T34	3007
all_pins[3]	transitions[0x1=>0x0]	78974	1		T1	1732		T21	1597		T24	1672
all_pins[4]	values[0x0]	200640	1		T1	1733		T2	2		T3	1
all_pins[4]	values[0x1]	106675	1		T1	1732		T21	1597		T24	1672
all_pins[4]	transitions[0x0=>0x1]	106654	1		T1	1732		T21	1597		T24	1672
all_pins[4]	transitions[0x1=>0x0]	35	1		T363	1		T364	2		T365	1
all_pins[5]	values[0x0]	307259	1		T1	3465		T2	2		T3	1
all_pins[5]	values[0x1]	56	1		T362	2		T363	1		T364	3
all_pins[5]	transitions[0x0=>0x1]	19	1		T362	1		T364	1		T395	1
all_pins[5]	transitions[0x1=>0x0]	107	1		T283	3		T284	3		T362	3