Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1		T283	4		T284	4		T362	7
all_values[1]	275	1		T283	4		T284	4		T362	7
all_values[2]	275	1		T283	4		T284	4		T362	7
all_values[3]	275	1		T283	4		T284	4		T362	7
all_values[4]	275	1		T283	4		T284	4		T362	7
all_values[5]	275	1		T283	4		T284	4		T362	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	920	1		T283	17		T284	12		T362	23
auto[1]	730	1		T283	7		T284	12		T362	19

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	549	1		T283	9		T284	9		T362	9
auto[1]	1101	1		T283	15		T284	15		T362	33

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	993	1		T283	19		T284	15		T362	19
auto[1]	657	1		T283	5		T284	9		T362	23

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	80	1		T283	1		T363	1		T364	3
all_values[0]	auto[0]	auto[1]	auto[1]	76	1		T283	3		T284	2		T362	1
all_values[0]	auto[1]	auto[0]	auto[1]	65	1		T362	3		T364	1		T365	2
all_values[0]	auto[1]	auto[1]	auto[1]	54	1		T284	2		T362	3		T363	1
all_values[1]	auto[0]	auto[0]	auto[1]	96	1		T283	3		T284	1		T362	2
all_values[1]	auto[0]	auto[1]	auto[1]	74	1		T284	2		T362	2		T363	1
all_values[1]	auto[1]	auto[0]	auto[1]	59	1		T362	2		T364	2		T366	2
all_values[1]	auto[1]	auto[1]	auto[1]	46	1		T283	1		T284	1		T362	1
all_values[2]	auto[0]	auto[0]	auto[0]	90	1		T283	3		T284	1		T362	2
all_values[2]	auto[0]	auto[1]	auto[0]	71	1		T363	2		T365	2		T366	2
all_values[2]	auto[1]	auto[0]	auto[1]	77	1		T284	3		T362	3		T363	1
all_values[2]	auto[1]	auto[1]	auto[1]	37	1		T283	1		T362	2		T364	1
all_values[3]	auto[0]	auto[0]	auto[0]	94	1		T283	2		T284	1		T362	2
all_values[3]	auto[0]	auto[1]	auto[0]	74	1		T283	2		T284	2		T362	3
all_values[3]	auto[1]	auto[0]	auto[1]	60	1		T284	1		T362	2		T363	2
all_values[3]	auto[1]	auto[1]	auto[1]	47	1		T364	1		T365	1		T366	1
all_values[4]	auto[0]	auto[0]	auto[0]	59	1		T283	1		T284	1		T363	1
all_values[4]	auto[0]	auto[0]	auto[1]	33	1		T283	2		T362	2		T363	1
all_values[4]	auto[0]	auto[1]	auto[0]	51	1		T284	2		T364	1		T367	2
all_values[4]	auto[0]	auto[1]	auto[1]	26	1		T362	2		T364	1		T366	1
all_values[4]	auto[1]	auto[0]	auto[1]	62	1		T283	1		T362	1		T363	2
all_values[4]	auto[1]	auto[1]	auto[1]	44	1		T284	1		T362	2		T364	1
all_values[5]	auto[0]	auto[0]	auto[0]	52	1		T283	1		T284	2		T362	1
all_values[5]	auto[0]	auto[0]	auto[1]	34	1		T283	1		T284	1		T364	1
all_values[5]	auto[0]	auto[1]	auto[0]	58	1		T362	1		T363	1		T364	1
all_values[5]	auto[0]	auto[1]	auto[1]	25	1		T362	1		T363	1		T364	1
all_values[5]	auto[1]	auto[0]	auto[1]	59	1		T283	2		T284	1		T362	3
all_values[5]	auto[1]	auto[1]	auto[1]	47	1		T362	1		T363	1		T364	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal