| T1079 |
/workspace/coverage/default/0.flash_ctrl_host_addr_infection.279498089 |
|
|
Jul 18 04:53:43 PM PDT 24 |
Jul 18 04:54:15 PM PDT 24 |
75279200 ps |
| T1080 |
/workspace/coverage/default/35.flash_ctrl_intr_rd.3845477952 |
|
|
Jul 18 05:05:18 PM PDT 24 |
Jul 18 05:07:53 PM PDT 24 |
1721966700 ps |
| T1081 |
/workspace/coverage/default/22.flash_ctrl_prog_reset.1752821973 |
|
|
Jul 18 05:01:36 PM PDT 24 |
Jul 18 05:01:51 PM PDT 24 |
20416700 ps |
| T1082 |
/workspace/coverage/default/1.flash_ctrl_prog_reset.3118528514 |
|
|
Jul 18 04:52:56 PM PDT 24 |
Jul 18 04:55:53 PM PDT 24 |
3709950700 ps |
| T1083 |
/workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.441418921 |
|
|
Jul 18 04:53:42 PM PDT 24 |
Jul 18 04:55:00 PM PDT 24 |
10022155700 ps |
| T1084 |
/workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.339871285 |
|
|
Jul 18 04:56:50 PM PDT 24 |
Jul 18 04:57:20 PM PDT 24 |
42867400 ps |
| T1085 |
/workspace/coverage/default/11.flash_ctrl_rw.504061824 |
|
|
Jul 18 04:58:33 PM PDT 24 |
Jul 18 05:07:38 PM PDT 24 |
8180354500 ps |
| T1086 |
/workspace/coverage/default/73.flash_ctrl_connect.1169095207 |
|
|
Jul 18 05:10:38 PM PDT 24 |
Jul 18 05:10:54 PM PDT 24 |
13890000 ps |
| T1087 |
/workspace/coverage/default/46.flash_ctrl_smoke.193291549 |
|
|
Jul 18 05:10:03 PM PDT 24 |
Jul 18 05:11:46 PM PDT 24 |
22830700 ps |
| T1088 |
/workspace/coverage/default/6.flash_ctrl_ro.1677095060 |
|
|
Jul 18 04:56:04 PM PDT 24 |
Jul 18 04:58:33 PM PDT 24 |
1136797600 ps |
| T1089 |
/workspace/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.1007121610 |
|
|
Jul 18 04:59:46 PM PDT 24 |
Jul 18 05:00:38 PM PDT 24 |
10040018000 ps |
| T1090 |
/workspace/coverage/default/37.flash_ctrl_disable.4069437132 |
|
|
Jul 18 05:07:13 PM PDT 24 |
Jul 18 05:07:37 PM PDT 24 |
10399400 ps |
| T392 |
/workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.218859835 |
|
|
Jul 18 04:57:04 PM PDT 24 |
Jul 18 04:57:33 PM PDT 24 |
66994900 ps |
| T1091 |
/workspace/coverage/default/5.flash_ctrl_prog_reset.1897796850 |
|
|
Jul 18 04:55:31 PM PDT 24 |
Jul 18 04:59:04 PM PDT 24 |
11309075500 ps |
| T1092 |
/workspace/coverage/default/57.flash_ctrl_connect.2647421818 |
|
|
Jul 18 05:10:25 PM PDT 24 |
Jul 18 05:10:40 PM PDT 24 |
13266600 ps |
| T1093 |
/workspace/coverage/default/1.flash_ctrl_smoke_hw.948270279 |
|
|
Jul 18 04:52:35 PM PDT 24 |
Jul 18 04:53:02 PM PDT 24 |
34257500 ps |
| T1094 |
/workspace/coverage/default/7.flash_ctrl_hw_rma_reset.540112316 |
|
|
Jul 18 04:56:05 PM PDT 24 |
Jul 18 05:11:06 PM PDT 24 |
190228193100 ps |
| T1095 |
/workspace/coverage/default/5.flash_ctrl_sec_info_access.865759733 |
|
|
Jul 18 04:55:33 PM PDT 24 |
Jul 18 04:56:44 PM PDT 24 |
2728105300 ps |
| T1096 |
/workspace/coverage/default/18.flash_ctrl_hw_rma_reset.506386439 |
|
|
Jul 18 05:00:13 PM PDT 24 |
Jul 18 05:15:02 PM PDT 24 |
40123959900 ps |
| T1097 |
/workspace/coverage/default/6.flash_ctrl_rw_evict.3441871678 |
|
|
Jul 18 04:56:05 PM PDT 24 |
Jul 18 04:56:36 PM PDT 24 |
60096000 ps |
| T1098 |
/workspace/coverage/default/32.flash_ctrl_otp_reset.634609304 |
|
|
Jul 18 05:03:58 PM PDT 24 |
Jul 18 05:05:49 PM PDT 24 |
40845600 ps |
| T1099 |
/workspace/coverage/default/2.flash_ctrl_mp_regions.446597027 |
|
|
Jul 18 04:53:04 PM PDT 24 |
Jul 18 04:56:51 PM PDT 24 |
7569601200 ps |
| T1100 |
/workspace/coverage/default/0.flash_ctrl_prog_reset.2246912482 |
|
|
Jul 18 04:52:21 PM PDT 24 |
Jul 18 04:55:24 PM PDT 24 |
8151632400 ps |
| T1101 |
/workspace/coverage/default/1.flash_ctrl_error_prog_type.415472121 |
|
|
Jul 18 04:52:36 PM PDT 24 |
Jul 18 05:30:46 PM PDT 24 |
806096600 ps |
| T1102 |
/workspace/coverage/default/23.flash_ctrl_prog_reset.2947554108 |
|
|
Jul 18 05:01:21 PM PDT 24 |
Jul 18 05:01:36 PM PDT 24 |
69290000 ps |
| T1103 |
/workspace/coverage/default/19.flash_ctrl_wo.881276422 |
|
|
Jul 18 05:00:33 PM PDT 24 |
Jul 18 05:03:14 PM PDT 24 |
1802702800 ps |
| T1104 |
/workspace/coverage/default/1.flash_ctrl_intr_rd.3156436380 |
|
|
Jul 18 04:52:51 PM PDT 24 |
Jul 18 04:56:08 PM PDT 24 |
2221950000 ps |
| T1105 |
/workspace/coverage/default/39.flash_ctrl_intr_rd.3101602388 |
|
|
Jul 18 05:07:12 PM PDT 24 |
Jul 18 05:09:35 PM PDT 24 |
659160700 ps |
| T1106 |
/workspace/coverage/default/6.flash_ctrl_otp_reset.2895366294 |
|
|
Jul 18 04:55:33 PM PDT 24 |
Jul 18 04:57:47 PM PDT 24 |
142397900 ps |
| T1107 |
/workspace/coverage/default/64.flash_ctrl_otp_reset.3159411947 |
|
|
Jul 18 05:10:31 PM PDT 24 |
Jul 18 05:12:43 PM PDT 24 |
37926700 ps |
| T1108 |
/workspace/coverage/default/7.flash_ctrl_ro.1884957908 |
|
|
Jul 18 04:56:27 PM PDT 24 |
Jul 18 04:58:33 PM PDT 24 |
2051239400 ps |
| T1109 |
/workspace/coverage/default/11.flash_ctrl_phy_arb.204418843 |
|
|
Jul 18 04:58:28 PM PDT 24 |
Jul 18 04:59:39 PM PDT 24 |
121723800 ps |
| T1110 |
/workspace/coverage/default/13.flash_ctrl_hw_sec_otp.3757337901 |
|
|
Jul 18 04:58:45 PM PDT 24 |
Jul 18 05:01:25 PM PDT 24 |
5270354600 ps |
| T1111 |
/workspace/coverage/default/18.flash_ctrl_alert_test.3131805024 |
|
|
Jul 18 05:00:34 PM PDT 24 |
Jul 18 05:00:49 PM PDT 24 |
100284100 ps |
| T1112 |
/workspace/coverage/default/6.flash_ctrl_prog_reset.1478243341 |
|
|
Jul 18 04:56:06 PM PDT 24 |
Jul 18 04:56:22 PM PDT 24 |
177326700 ps |
| T1113 |
/workspace/coverage/default/46.flash_ctrl_connect.2851707852 |
|
|
Jul 18 05:10:09 PM PDT 24 |
Jul 18 05:10:26 PM PDT 24 |
29320100 ps |
| T1114 |
/workspace/coverage/default/6.flash_ctrl_error_prog_win.4156740399 |
|
|
Jul 18 04:55:32 PM PDT 24 |
Jul 18 05:10:46 PM PDT 24 |
1835072700 ps |
| T1115 |
/workspace/coverage/default/43.flash_ctrl_alert_test.544105820 |
|
|
Jul 18 05:10:03 PM PDT 24 |
Jul 18 05:10:17 PM PDT 24 |
24250000 ps |
| T1116 |
/workspace/coverage/default/41.flash_ctrl_disable.2563100148 |
|
|
Jul 18 05:07:15 PM PDT 24 |
Jul 18 05:07:37 PM PDT 24 |
64174700 ps |
| T58 |
/workspace/coverage/default/0.flash_ctrl_sec_cm.3450243063 |
|
|
Jul 18 04:52:23 PM PDT 24 |
Jul 18 06:11:46 PM PDT 24 |
3983957800 ps |
| T1117 |
/workspace/coverage/default/48.flash_ctrl_hw_sec_otp.3111166624 |
|
|
Jul 18 05:10:22 PM PDT 24 |
Jul 18 05:13:35 PM PDT 24 |
2676275200 ps |
| T1118 |
/workspace/coverage/default/74.flash_ctrl_otp_reset.1009951298 |
|
|
Jul 18 05:10:39 PM PDT 24 |
Jul 18 05:12:55 PM PDT 24 |
82313400 ps |
| T1119 |
/workspace/coverage/default/43.flash_ctrl_disable.3864112120 |
|
|
Jul 18 05:09:57 PM PDT 24 |
Jul 18 05:10:19 PM PDT 24 |
15785300 ps |
| T1120 |
/workspace/coverage/default/10.flash_ctrl_ro.998809013 |
|
|
Jul 18 04:57:38 PM PDT 24 |
Jul 18 04:59:52 PM PDT 24 |
1264622400 ps |
| T1121 |
/workspace/coverage/default/7.flash_ctrl_wo.414869845 |
|
|
Jul 18 04:56:29 PM PDT 24 |
Jul 18 05:00:19 PM PDT 24 |
18116707200 ps |
| T1122 |
/workspace/coverage/default/37.flash_ctrl_intr_rd.3375427439 |
|
|
Jul 18 05:06:49 PM PDT 24 |
Jul 18 05:10:24 PM PDT 24 |
1495579000 ps |
| T1123 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2111516589 |
|
|
Jul 18 04:47:38 PM PDT 24 |
Jul 18 04:47:52 PM PDT 24 |
14209600 ps |
| T283 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1158016702 |
|
|
Jul 18 04:48:32 PM PDT 24 |
Jul 18 04:48:48 PM PDT 24 |
214982100 ps |
| T65 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3285572767 |
|
|
Jul 18 04:47:50 PM PDT 24 |
Jul 18 04:48:36 PM PDT 24 |
2237672100 ps |
| T284 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.4165454113 |
|
|
Jul 18 04:48:44 PM PDT 24 |
Jul 18 04:48:59 PM PDT 24 |
39165800 ps |
| T66 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3439612638 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:48:58 PM PDT 24 |
20765500 ps |
| T67 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1444080228 |
|
|
Jul 18 04:48:19 PM PDT 24 |
Jul 18 04:48:36 PM PDT 24 |
64623200 ps |
| T106 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1390366716 |
|
|
Jul 18 04:48:30 PM PDT 24 |
Jul 18 04:48:47 PM PDT 24 |
37696400 ps |
| T105 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.581110329 |
|
|
Jul 18 04:48:16 PM PDT 24 |
Jul 18 04:48:35 PM PDT 24 |
27060800 ps |
| T209 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2400006009 |
|
|
Jul 18 04:48:09 PM PDT 24 |
Jul 18 04:48:41 PM PDT 24 |
62834900 ps |
| T102 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2421236279 |
|
|
Jul 18 04:48:19 PM PDT 24 |
Jul 18 04:48:39 PM PDT 24 |
53898700 ps |
| T1124 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.922560587 |
|
|
Jul 18 04:48:26 PM PDT 24 |
Jul 18 04:48:43 PM PDT 24 |
19001100 ps |
| T1125 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3357633864 |
|
|
Jul 18 04:48:31 PM PDT 24 |
Jul 18 04:48:48 PM PDT 24 |
67624700 ps |
| T103 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3698198961 |
|
|
Jul 18 04:48:30 PM PDT 24 |
Jul 18 04:48:47 PM PDT 24 |
337538300 ps |
| T276 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2771971845 |
|
|
Jul 18 04:47:50 PM PDT 24 |
Jul 18 04:48:36 PM PDT 24 |
76611100 ps |
| T1126 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.888028238 |
|
|
Jul 18 04:48:41 PM PDT 24 |
Jul 18 04:48:58 PM PDT 24 |
18869400 ps |
| T1127 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3433910363 |
|
|
Jul 18 04:48:32 PM PDT 24 |
Jul 18 04:48:50 PM PDT 24 |
92108800 ps |
| T362 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3130367711 |
|
|
Jul 18 04:48:39 PM PDT 24 |
Jul 18 04:48:55 PM PDT 24 |
20957400 ps |
| T104 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.578689754 |
|
|
Jul 18 04:47:36 PM PDT 24 |
Jul 18 04:47:53 PM PDT 24 |
27513800 ps |
| T206 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3915173551 |
|
|
Jul 18 04:48:20 PM PDT 24 |
Jul 18 05:03:33 PM PDT 24 |
1264709800 ps |
| T1128 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1923650570 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:48:54 PM PDT 24 |
34619100 ps |
| T252 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.627476205 |
|
|
Jul 18 04:48:16 PM PDT 24 |
Jul 18 04:48:37 PM PDT 24 |
174732300 ps |
| T363 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.517752068 |
|
|
Jul 18 04:48:44 PM PDT 24 |
Jul 18 04:48:59 PM PDT 24 |
43539500 ps |
| T253 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.805531097 |
|
|
Jul 18 04:48:28 PM PDT 24 |
Jul 18 04:48:48 PM PDT 24 |
360620300 ps |
| T1129 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1696475180 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:48:54 PM PDT 24 |
40271400 ps |
| T207 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.450887965 |
|
|
Jul 18 04:48:31 PM PDT 24 |
Jul 18 04:48:49 PM PDT 24 |
28909700 ps |
| T364 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.4286478595 |
|
|
Jul 18 04:48:34 PM PDT 24 |
Jul 18 04:48:50 PM PDT 24 |
56537600 ps |
| T365 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.1929813890 |
|
|
Jul 18 04:48:44 PM PDT 24 |
Jul 18 04:48:59 PM PDT 24 |
22701300 ps |
| T366 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1228521546 |
|
|
Jul 18 04:48:15 PM PDT 24 |
Jul 18 04:48:30 PM PDT 24 |
17282400 ps |
| T277 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1468268367 |
|
|
Jul 18 04:48:32 PM PDT 24 |
Jul 18 04:48:50 PM PDT 24 |
1291850300 ps |
| T1130 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1336468715 |
|
|
Jul 18 04:47:50 PM PDT 24 |
Jul 18 04:48:06 PM PDT 24 |
13142200 ps |
| T1131 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1116887203 |
|
|
Jul 18 04:48:34 PM PDT 24 |
Jul 18 04:48:53 PM PDT 24 |
11122900 ps |
| T1132 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2318615076 |
|
|
Jul 18 04:48:27 PM PDT 24 |
Jul 18 04:48:44 PM PDT 24 |
14796000 ps |
| T208 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3370050891 |
|
|
Jul 18 04:48:37 PM PDT 24 |
Jul 18 04:49:00 PM PDT 24 |
278210700 ps |
| T1133 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1349536404 |
|
|
Jul 18 04:47:46 PM PDT 24 |
Jul 18 04:48:04 PM PDT 24 |
20139700 ps |
| T255 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3149450616 |
|
|
Jul 18 04:48:39 PM PDT 24 |
Jul 18 04:56:24 PM PDT 24 |
3731920500 ps |
| T328 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.983041887 |
|
|
Jul 18 04:48:16 PM PDT 24 |
Jul 18 04:48:35 PM PDT 24 |
193154800 ps |
| T395 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1919998778 |
|
|
Jul 18 04:48:50 PM PDT 24 |
Jul 18 04:49:06 PM PDT 24 |
15042000 ps |
| T254 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3631447987 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:48:58 PM PDT 24 |
28305300 ps |
| T259 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1427379023 |
|
|
Jul 18 04:47:38 PM PDT 24 |
Jul 18 04:47:53 PM PDT 24 |
18083900 ps |
| T322 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1908651528 |
|
|
Jul 18 04:48:29 PM PDT 24 |
Jul 18 04:48:46 PM PDT 24 |
44906300 ps |
| T273 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2711912780 |
|
|
Jul 18 04:48:34 PM PDT 24 |
Jul 18 04:54:58 PM PDT 24 |
1471346700 ps |
| T256 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3828209124 |
|
|
Jul 18 04:48:32 PM PDT 24 |
Jul 18 05:03:38 PM PDT 24 |
401393000 ps |
| T280 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1307039533 |
|
|
Jul 18 04:48:24 PM PDT 24 |
Jul 18 04:56:01 PM PDT 24 |
1965605600 ps |
| T1134 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.931875273 |
|
|
Jul 18 04:48:15 PM PDT 24 |
Jul 18 04:49:19 PM PDT 24 |
2428511000 ps |
| T1135 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3807319709 |
|
|
Jul 18 04:48:28 PM PDT 24 |
Jul 18 04:48:42 PM PDT 24 |
61077500 ps |
| T1136 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1539589618 |
|
|
Jul 18 04:48:37 PM PDT 24 |
Jul 18 04:48:56 PM PDT 24 |
213330200 ps |
| T1137 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1642239110 |
|
|
Jul 18 04:48:17 PM PDT 24 |
Jul 18 04:48:35 PM PDT 24 |
11704600 ps |
| T1138 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3909262726 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:48:54 PM PDT 24 |
95070500 ps |
| T1139 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.843009215 |
|
|
Jul 18 04:48:42 PM PDT 24 |
Jul 18 04:48:59 PM PDT 24 |
68407800 ps |
| T367 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2368410554 |
|
|
Jul 18 04:48:28 PM PDT 24 |
Jul 18 04:48:43 PM PDT 24 |
53646400 ps |
| T1140 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2422799912 |
|
|
Jul 18 04:47:49 PM PDT 24 |
Jul 18 04:48:08 PM PDT 24 |
99400800 ps |
| T1141 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2768602193 |
|
|
Jul 18 04:48:33 PM PDT 24 |
Jul 18 04:48:52 PM PDT 24 |
50077700 ps |
| T1142 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.4006605116 |
|
|
Jul 18 04:48:32 PM PDT 24 |
Jul 18 04:48:50 PM PDT 24 |
43071600 ps |
| T260 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.630591244 |
|
|
Jul 18 04:47:49 PM PDT 24 |
Jul 18 04:48:03 PM PDT 24 |
16403900 ps |
| T278 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1576764399 |
|
|
Jul 18 04:48:31 PM PDT 24 |
Jul 18 04:48:51 PM PDT 24 |
149825800 ps |
| T293 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.796680902 |
|
|
Jul 18 04:48:17 PM PDT 24 |
Jul 18 04:48:35 PM PDT 24 |
32773400 ps |
| T1143 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2734509119 |
|
|
Jul 18 04:47:32 PM PDT 24 |
Jul 18 04:47:47 PM PDT 24 |
15805400 ps |
| T1144 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2819588668 |
|
|
Jul 18 04:48:32 PM PDT 24 |
Jul 18 04:48:48 PM PDT 24 |
55101400 ps |
| T1145 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1174799194 |
|
|
Jul 18 04:48:33 PM PDT 24 |
Jul 18 04:48:51 PM PDT 24 |
33019100 ps |
| T1146 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.436437213 |
|
|
Jul 18 04:48:17 PM PDT 24 |
Jul 18 04:49:16 PM PDT 24 |
4690659400 ps |
| T1147 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3697185484 |
|
|
Jul 18 04:48:18 PM PDT 24 |
Jul 18 04:48:36 PM PDT 24 |
28219400 ps |
| T329 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1596940794 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:48:58 PM PDT 24 |
84166700 ps |
| T1148 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.381227141 |
|
|
Jul 18 04:48:16 PM PDT 24 |
Jul 18 04:48:34 PM PDT 24 |
73458200 ps |
| T1149 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2719985261 |
|
|
Jul 18 04:48:45 PM PDT 24 |
Jul 18 04:49:01 PM PDT 24 |
87768700 ps |
| T291 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1845095157 |
|
|
Jul 18 04:48:13 PM PDT 24 |
Jul 18 04:55:57 PM PDT 24 |
1377808500 ps |
| T1150 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1391778534 |
|
|
Jul 18 04:48:45 PM PDT 24 |
Jul 18 04:49:01 PM PDT 24 |
50444800 ps |
| T1151 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2225940855 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:48:54 PM PDT 24 |
50954500 ps |
| T1152 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.2256620621 |
|
|
Jul 18 04:48:44 PM PDT 24 |
Jul 18 04:48:59 PM PDT 24 |
17923800 ps |
| T1153 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3108693418 |
|
|
Jul 18 04:48:16 PM PDT 24 |
Jul 18 04:48:33 PM PDT 24 |
15148900 ps |
| T289 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2192736748 |
|
|
Jul 18 04:48:20 PM PDT 24 |
Jul 18 04:48:41 PM PDT 24 |
54165100 ps |
| T1154 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.28732182 |
|
|
Jul 18 04:48:26 PM PDT 24 |
Jul 18 04:48:40 PM PDT 24 |
27154900 ps |
| T1155 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.4109239916 |
|
|
Jul 18 04:48:44 PM PDT 24 |
Jul 18 04:48:59 PM PDT 24 |
54002800 ps |
| T292 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2395236003 |
|
|
Jul 18 04:48:35 PM PDT 24 |
Jul 18 04:48:54 PM PDT 24 |
209919200 ps |
| T1156 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2367251350 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:49:00 PM PDT 24 |
96168000 ps |
| T323 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.2335992105 |
|
|
Jul 18 04:48:13 PM PDT 24 |
Jul 18 04:48:31 PM PDT 24 |
401980800 ps |
| T279 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.3961341518 |
|
|
Jul 18 04:48:13 PM PDT 24 |
Jul 18 04:48:30 PM PDT 24 |
81012600 ps |
| T1157 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.4037946082 |
|
|
Jul 18 04:47:49 PM PDT 24 |
Jul 18 04:48:05 PM PDT 24 |
59090700 ps |
| T400 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.826006239 |
|
|
Jul 18 04:48:16 PM PDT 24 |
Jul 18 04:55:56 PM PDT 24 |
1510200400 ps |
| T1158 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.3557734738 |
|
|
Jul 18 04:48:45 PM PDT 24 |
Jul 18 04:49:01 PM PDT 24 |
55636100 ps |
| T1159 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.4045313357 |
|
|
Jul 18 04:48:36 PM PDT 24 |
Jul 18 04:48:55 PM PDT 24 |
68216900 ps |
| T1160 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2547677353 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:48:54 PM PDT 24 |
16157600 ps |
| T1161 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2661056535 |
|
|
Jul 18 04:48:20 PM PDT 24 |
Jul 18 04:48:35 PM PDT 24 |
11812900 ps |
| T1162 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3142838338 |
|
|
Jul 18 04:48:09 PM PDT 24 |
Jul 18 04:48:27 PM PDT 24 |
19087900 ps |
| T1163 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.3184298748 |
|
|
Jul 18 04:48:37 PM PDT 24 |
Jul 18 04:48:53 PM PDT 24 |
15929300 ps |
| T286 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.210849227 |
|
|
Jul 18 04:48:10 PM PDT 24 |
Jul 18 04:48:27 PM PDT 24 |
60263600 ps |
| T1164 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1933218000 |
|
|
Jul 18 04:48:33 PM PDT 24 |
Jul 18 04:48:49 PM PDT 24 |
53459300 ps |
| T1165 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2591235369 |
|
|
Jul 18 04:47:41 PM PDT 24 |
Jul 18 04:47:56 PM PDT 24 |
27399900 ps |
| T1166 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3196349029 |
|
|
Jul 18 04:48:13 PM PDT 24 |
Jul 18 04:48:28 PM PDT 24 |
18045000 ps |
| T324 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1001194201 |
|
|
Jul 18 04:47:49 PM PDT 24 |
Jul 18 04:48:07 PM PDT 24 |
84785600 ps |
| T285 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3706516925 |
|
|
Jul 18 04:48:35 PM PDT 24 |
Jul 18 04:56:14 PM PDT 24 |
755113000 ps |
| T287 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3825485916 |
|
|
Jul 18 04:48:34 PM PDT 24 |
Jul 18 04:48:57 PM PDT 24 |
296261000 ps |
| T1167 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3927956910 |
|
|
Jul 18 04:48:13 PM PDT 24 |
Jul 18 04:48:32 PM PDT 24 |
44594700 ps |
| T1168 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1868007129 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:48:57 PM PDT 24 |
44040200 ps |
| T1169 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2123533742 |
|
|
Jul 18 04:48:15 PM PDT 24 |
Jul 18 04:48:30 PM PDT 24 |
27195800 ps |
| T325 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.850519663 |
|
|
Jul 18 04:48:31 PM PDT 24 |
Jul 18 04:48:49 PM PDT 24 |
220584600 ps |
| T1170 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.940526133 |
|
|
Jul 18 04:47:36 PM PDT 24 |
Jul 18 04:47:53 PM PDT 24 |
14382100 ps |
| T1171 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3726278169 |
|
|
Jul 18 04:48:34 PM PDT 24 |
Jul 18 04:48:52 PM PDT 24 |
37945500 ps |
| T288 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3716917435 |
|
|
Jul 18 04:47:50 PM PDT 24 |
Jul 18 04:48:06 PM PDT 24 |
210090000 ps |
| T1172 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.521943744 |
|
|
Jul 18 04:48:46 PM PDT 24 |
Jul 18 04:49:03 PM PDT 24 |
54824600 ps |
| T1173 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.2789595322 |
|
|
Jul 18 04:48:30 PM PDT 24 |
Jul 18 04:48:44 PM PDT 24 |
19855500 ps |
| T1174 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3542106781 |
|
|
Jul 18 04:48:34 PM PDT 24 |
Jul 18 04:48:52 PM PDT 24 |
40725100 ps |
| T1175 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.375409791 |
|
|
Jul 18 04:48:29 PM PDT 24 |
Jul 18 04:48:47 PM PDT 24 |
36616900 ps |
| T1176 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2845716931 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:49:02 PM PDT 24 |
601639900 ps |
| T1177 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1771902799 |
|
|
Jul 18 04:48:39 PM PDT 24 |
Jul 18 04:48:58 PM PDT 24 |
51974800 ps |
| T1178 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1174028881 |
|
|
Jul 18 04:48:36 PM PDT 24 |
Jul 18 04:48:52 PM PDT 24 |
80657700 ps |
| T1179 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2474242889 |
|
|
Jul 18 04:48:16 PM PDT 24 |
Jul 18 04:48:32 PM PDT 24 |
26277700 ps |
| T261 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3902977280 |
|
|
Jul 18 04:48:10 PM PDT 24 |
Jul 18 04:48:25 PM PDT 24 |
27966300 ps |
| T1180 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.3617032457 |
|
|
Jul 18 04:48:46 PM PDT 24 |
Jul 18 04:49:01 PM PDT 24 |
15014000 ps |
| T1181 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.55471683 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:48:54 PM PDT 24 |
43113500 ps |
| T1182 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.194173209 |
|
|
Jul 18 04:48:49 PM PDT 24 |
Jul 18 04:49:05 PM PDT 24 |
47057600 ps |
| T1183 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2139593044 |
|
|
Jul 18 04:48:42 PM PDT 24 |
Jul 18 04:48:59 PM PDT 24 |
15795900 ps |
| T1184 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1180554661 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:48:56 PM PDT 24 |
18050800 ps |
| T1185 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1591475111 |
|
|
Jul 18 04:48:15 PM PDT 24 |
Jul 18 04:48:37 PM PDT 24 |
302206200 ps |
| T1186 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1797626804 |
|
|
Jul 18 04:48:11 PM PDT 24 |
Jul 18 04:48:27 PM PDT 24 |
44273800 ps |
| T1187 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.380039830 |
|
|
Jul 18 04:48:45 PM PDT 24 |
Jul 18 04:49:00 PM PDT 24 |
58016300 ps |
| T396 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1877399155 |
|
|
Jul 18 04:48:36 PM PDT 24 |
Jul 18 05:03:45 PM PDT 24 |
649507600 ps |
| T326 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1442285310 |
|
|
Jul 18 04:48:37 PM PDT 24 |
Jul 18 04:48:54 PM PDT 24 |
41939700 ps |
| T281 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1887779336 |
|
|
Jul 18 04:48:28 PM PDT 24 |
Jul 18 04:48:49 PM PDT 24 |
231339400 ps |
| T1188 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1240221540 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:49:00 PM PDT 24 |
97881600 ps |
| T1189 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.159523249 |
|
|
Jul 18 04:48:17 PM PDT 24 |
Jul 18 04:48:35 PM PDT 24 |
90633800 ps |
| T1190 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2100028139 |
|
|
Jul 18 04:48:18 PM PDT 24 |
Jul 18 04:48:36 PM PDT 24 |
38900900 ps |
| T1191 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2580769587 |
|
|
Jul 18 04:48:11 PM PDT 24 |
Jul 18 04:48:29 PM PDT 24 |
177915500 ps |
| T398 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.1837165331 |
|
|
Jul 18 04:48:21 PM PDT 24 |
Jul 18 05:01:04 PM PDT 24 |
11234217200 ps |
| T1192 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.3820686512 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:48:54 PM PDT 24 |
54670600 ps |
| T1193 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2319005502 |
|
|
Jul 18 04:48:36 PM PDT 24 |
Jul 18 04:48:57 PM PDT 24 |
84013200 ps |
| T1194 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.697699947 |
|
|
Jul 18 04:47:46 PM PDT 24 |
Jul 18 04:48:07 PM PDT 24 |
318925500 ps |
| T1195 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3435381760 |
|
|
Jul 18 04:48:27 PM PDT 24 |
Jul 18 04:48:44 PM PDT 24 |
19099300 ps |
| T1196 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3699215509 |
|
|
Jul 18 04:48:11 PM PDT 24 |
Jul 18 04:48:25 PM PDT 24 |
49969500 ps |
| T1197 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1776651788 |
|
|
Jul 18 04:48:31 PM PDT 24 |
Jul 18 04:48:45 PM PDT 24 |
14050100 ps |
| T1198 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.281676501 |
|
|
Jul 18 04:47:46 PM PDT 24 |
Jul 18 04:48:07 PM PDT 24 |
608820500 ps |
| T296 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1234332231 |
|
|
Jul 18 04:48:15 PM PDT 24 |
Jul 18 04:48:33 PM PDT 24 |
78418100 ps |
| T1199 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3280974761 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:49:01 PM PDT 24 |
48295500 ps |
| T1200 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3398356675 |
|
|
Jul 18 04:48:37 PM PDT 24 |
Jul 18 04:48:55 PM PDT 24 |
11513200 ps |
| T290 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.130429710 |
|
|
Jul 18 04:47:38 PM PDT 24 |
Jul 18 04:47:55 PM PDT 24 |
64142300 ps |
| T402 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2263631533 |
|
|
Jul 18 04:48:17 PM PDT 24 |
Jul 18 04:55:55 PM PDT 24 |
365896300 ps |
| T1201 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1346559649 |
|
|
Jul 18 04:48:37 PM PDT 24 |
Jul 18 04:48:53 PM PDT 24 |
11598800 ps |
| T327 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1776404831 |
|
|
Jul 18 04:48:18 PM PDT 24 |
Jul 18 04:48:39 PM PDT 24 |
215496300 ps |
| T1202 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.170368535 |
|
|
Jul 18 04:48:45 PM PDT 24 |
Jul 18 04:49:00 PM PDT 24 |
30678200 ps |
| T397 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2632723081 |
|
|
Jul 18 04:47:49 PM PDT 24 |
Jul 18 04:54:17 PM PDT 24 |
257446600 ps |
| T1203 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3467312527 |
|
|
Jul 18 04:48:16 PM PDT 24 |
Jul 18 04:48:35 PM PDT 24 |
57002800 ps |
| T330 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.4171549922 |
|
|
Jul 18 04:48:41 PM PDT 24 |
Jul 18 04:48:59 PM PDT 24 |
367314200 ps |
| T1204 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2334191014 |
|
|
Jul 18 04:47:45 PM PDT 24 |
Jul 18 04:48:53 PM PDT 24 |
3755725600 ps |
| T1205 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1622567638 |
|
|
Jul 18 04:57:25 PM PDT 24 |
Jul 18 04:57:42 PM PDT 24 |
43741700 ps |
| T1206 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1162514300 |
|
|
Jul 18 04:48:18 PM PDT 24 |
Jul 18 04:48:36 PM PDT 24 |
16975800 ps |
| T1207 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.3772672378 |
|
|
Jul 18 04:48:42 PM PDT 24 |
Jul 18 04:48:57 PM PDT 24 |
16309100 ps |
| T1208 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2081694645 |
|
|
Jul 18 04:48:14 PM PDT 24 |
Jul 18 04:48:31 PM PDT 24 |
380493300 ps |
| T1209 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.711097682 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:48:53 PM PDT 24 |
44621300 ps |
| T1210 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3803923280 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:48:56 PM PDT 24 |
37867000 ps |
| T1211 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3802139346 |
|
|
Jul 18 04:48:45 PM PDT 24 |
Jul 18 04:49:00 PM PDT 24 |
90254000 ps |
| T1212 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1584383029 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:49:00 PM PDT 24 |
112521800 ps |
| T1213 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3598433948 |
|
|
Jul 18 04:48:12 PM PDT 24 |
Jul 18 04:48:30 PM PDT 24 |
62807800 ps |
| T1214 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2709519717 |
|
|
Jul 18 04:48:19 PM PDT 24 |
Jul 18 04:48:37 PM PDT 24 |
160248200 ps |
| T1215 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1605717222 |
|
|
Jul 18 04:48:33 PM PDT 24 |
Jul 18 04:49:10 PM PDT 24 |
348806900 ps |
| T282 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.4145951846 |
|
|
Jul 18 04:48:42 PM PDT 24 |
Jul 18 04:49:01 PM PDT 24 |
174121000 ps |
| T1216 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.4014315623 |
|
|
Jul 18 04:48:28 PM PDT 24 |
Jul 18 04:48:47 PM PDT 24 |
79485700 ps |
| T1217 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.4066590505 |
|
|
Jul 18 04:48:44 PM PDT 24 |
Jul 18 04:48:59 PM PDT 24 |
151151500 ps |
| T1218 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.3340774047 |
|
|
Jul 18 04:47:46 PM PDT 24 |
Jul 18 04:48:01 PM PDT 24 |
16078800 ps |
| T1219 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.525989263 |
|
|
Jul 18 04:47:36 PM PDT 24 |
Jul 18 04:47:56 PM PDT 24 |
62219000 ps |
| T1220 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.76194878 |
|
|
Jul 18 04:48:19 PM PDT 24 |
Jul 18 04:48:35 PM PDT 24 |
17056600 ps |
| T399 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3498995711 |
|
|
Jul 18 04:48:33 PM PDT 24 |
Jul 18 04:56:15 PM PDT 24 |
836376300 ps |
| T1221 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1178974348 |
|
|
Jul 18 04:48:26 PM PDT 24 |
Jul 18 04:48:41 PM PDT 24 |
44138500 ps |
| T401 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2110661083 |
|
|
Jul 18 04:48:12 PM PDT 24 |
Jul 18 05:03:19 PM PDT 24 |
3108143200 ps |
| T403 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1632171353 |
|
|
Jul 18 04:48:32 PM PDT 24 |
Jul 18 04:56:11 PM PDT 24 |
387451700 ps |
| T1222 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.3229714788 |
|
|
Jul 18 04:48:18 PM PDT 24 |
Jul 18 04:48:33 PM PDT 24 |
16053600 ps |
| T1223 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3171816769 |
|
|
Jul 18 04:48:33 PM PDT 24 |
Jul 18 04:48:49 PM PDT 24 |
13077400 ps |
| T262 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1417765022 |
|
|
Jul 18 04:48:15 PM PDT 24 |
Jul 18 04:48:29 PM PDT 24 |
17435200 ps |
| T1224 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.3948682024 |
|
|
Jul 18 04:48:16 PM PDT 24 |
Jul 18 04:49:16 PM PDT 24 |
13178030500 ps |
| T1225 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3730782980 |
|
|
Jul 18 04:48:44 PM PDT 24 |
Jul 18 04:48:59 PM PDT 24 |
29444900 ps |
| T404 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.1180501941 |
|
|
Jul 18 04:48:35 PM PDT 24 |
Jul 18 05:03:23 PM PDT 24 |
352181800 ps |
| T1226 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2652726964 |
|
|
Jul 18 04:48:39 PM PDT 24 |
Jul 18 04:49:02 PM PDT 24 |
777111000 ps |
| T406 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.768193324 |
|
|
Jul 18 04:48:34 PM PDT 24 |
Jul 18 05:01:24 PM PDT 24 |
908126200 ps |
| T294 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.3909930598 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:49:00 PM PDT 24 |
102914300 ps |
| T1227 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3593593333 |
|
|
Jul 18 04:48:35 PM PDT 24 |
Jul 18 04:48:55 PM PDT 24 |
112413100 ps |
| T331 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.605699912 |
|
|
Jul 18 04:47:39 PM PDT 24 |
Jul 18 04:48:48 PM PDT 24 |
6801144700 ps |
| T1228 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2373145439 |
|
|
Jul 18 04:48:34 PM PDT 24 |
Jul 18 04:48:52 PM PDT 24 |
110592000 ps |
| T1229 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3346159167 |
|
|
Jul 18 04:47:45 PM PDT 24 |
Jul 18 04:48:06 PM PDT 24 |
249888500 ps |
| T295 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.576072820 |
|
|
Jul 18 04:48:20 PM PDT 24 |
Jul 18 04:48:39 PM PDT 24 |
78174500 ps |
| T1230 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.1737413553 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:48:54 PM PDT 24 |
55913000 ps |
| T1231 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.643127754 |
|
|
Jul 18 04:48:16 PM PDT 24 |
Jul 18 04:48:31 PM PDT 24 |
11870200 ps |
| T1232 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1814722250 |
|
|
Jul 18 04:48:09 PM PDT 24 |
Jul 18 04:48:26 PM PDT 24 |
38752100 ps |
| T1233 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.4248227484 |
|
|
Jul 18 04:48:34 PM PDT 24 |
Jul 18 04:48:49 PM PDT 24 |
49340600 ps |
| T1234 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3621837123 |
|
|
Jul 18 04:48:16 PM PDT 24 |
Jul 18 04:49:04 PM PDT 24 |
49388100 ps |
| T332 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2685043035 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:48:59 PM PDT 24 |
59444500 ps |
| T297 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2988001794 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 05:03:35 PM PDT 24 |
348493600 ps |
| T1235 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1132162129 |
|
|
Jul 18 04:48:33 PM PDT 24 |
Jul 18 04:48:53 PM PDT 24 |
79454700 ps |
| T1236 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3294376543 |
|
|
Jul 18 04:48:15 PM PDT 24 |
Jul 18 04:49:02 PM PDT 24 |
1154837000 ps |
| T1237 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3516607460 |
|
|
Jul 18 04:48:34 PM PDT 24 |
Jul 18 04:48:54 PM PDT 24 |
187835200 ps |
| T1238 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1649066343 |
|
|
Jul 18 04:48:45 PM PDT 24 |
Jul 18 04:49:00 PM PDT 24 |
58693900 ps |
| T1239 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.953460782 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:48:54 PM PDT 24 |
27575600 ps |
| T1240 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1428004361 |
|
|
Jul 18 04:48:15 PM PDT 24 |
Jul 18 04:48:30 PM PDT 24 |
28105100 ps |
| T263 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.4070671163 |
|
|
Jul 18 04:48:14 PM PDT 24 |
Jul 18 04:48:28 PM PDT 24 |
46661300 ps |
| T1241 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1001429425 |
|
|
Jul 18 04:47:49 PM PDT 24 |
Jul 18 04:48:45 PM PDT 24 |
712799000 ps |
| T1242 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1761047388 |
|
|
Jul 18 04:48:19 PM PDT 24 |
Jul 18 04:49:11 PM PDT 24 |
1717868800 ps |
| T1243 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2667871797 |
|
|
Jul 18 04:48:14 PM PDT 24 |
Jul 18 04:49:20 PM PDT 24 |
15636999900 ps |
| T1244 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1530845086 |
|
|
Jul 18 04:48:16 PM PDT 24 |
Jul 18 04:49:04 PM PDT 24 |
86582800 ps |
| T1245 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.380276242 |
|
|
Jul 18 04:48:18 PM PDT 24 |
Jul 18 04:48:34 PM PDT 24 |
69915700 ps |
| T405 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1989257268 |
|
|
Jul 18 04:47:36 PM PDT 24 |
Jul 18 04:54:02 PM PDT 24 |
230785200 ps |
| T1246 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.418931856 |
|
|
Jul 18 04:48:32 PM PDT 24 |
Jul 18 04:48:51 PM PDT 24 |
103571800 ps |
| T333 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.832706663 |
|
|
Jul 18 04:48:37 PM PDT 24 |
Jul 18 04:49:16 PM PDT 24 |
766733100 ps |
| T1247 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.1207098645 |
|
|
Jul 18 04:48:43 PM PDT 24 |
Jul 18 04:48:57 PM PDT 24 |
55755300 ps |
| T1248 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.2741561996 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:48:54 PM PDT 24 |
18064100 ps |
| T1249 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.291275148 |
|
|
Jul 18 04:48:31 PM PDT 24 |
Jul 18 04:48:49 PM PDT 24 |
35803100 ps |
| T334 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.818111390 |
|
|
Jul 18 04:48:38 PM PDT 24 |
Jul 18 04:48:58 PM PDT 24 |
369445700 ps |
| T1250 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.4193828943 |
|
|
Jul 18 04:48:17 PM PDT 24 |
Jul 18 04:48:48 PM PDT 24 |
76733500 ps |