Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	328613	1		T1	1		T2	2		T3	1
all_values[1]	328613	1		T1	1		T2	2		T3	1
all_values[2]	328613	1		T1	1		T2	2		T3	1
all_values[3]	328613	1		T1	1		T2	2		T3	1
all_values[4]	328613	1		T1	1		T2	2		T3	1
all_values[5]	328613	1		T1	1		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	663509	1		T1	6		T2	12		T3	6
auto[1]	1308169	1		T6	14072		T7	2552		T35	28400

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	963154	1		T1	4		T2	7		T3	4
auto[1]	1008524	1		T1	2		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	328440	1		T1	1		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	173	1		T269	2		T270	6		T271	2
all_values[1]	auto[0]	auto[1]	328461	1		T1	1		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	152	1		T270	2		T271	3		T335	3
all_values[2]	auto[0]	auto[0]	1589	1		T1	1		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	79	1		T269	2		T270	5		T271	1
all_values[2]	auto[1]	auto[0]	326885	1		T6	3518		T7	638		T35	7100
all_values[2]	auto[1]	auto[1]	60	1		T269	1		T271	2		T335	1
all_values[3]	auto[0]	auto[0]	1587	1		T1	1		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	76	1		T269	1		T270	1		T271	2
all_values[3]	auto[1]	auto[0]	89810	1		T6	1759		T7	319		T35	1775
all_values[3]	auto[1]	auto[1]	237140	1		T6	1759		T7	319		T35	5325
all_values[4]	auto[0]	auto[0]	1128	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	504	1		T2	1		T4	1		T18	1
all_values[4]	auto[1]	auto[0]	213704	1		T6	1759		T7	319		T35	5325
all_values[4]	auto[1]	auto[1]	113277	1		T6	1759		T7	319		T35	1775
all_values[5]	auto[0]	auto[0]	1538	1		T1	1		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	107	1		T37	1		T38	1		T131	1
all_values[5]	auto[1]	auto[0]	326913	1		T6	3518		T7	638		T35	7100
all_values[5]	auto[1]	auto[1]	55	1		T270	1		T271	1		T339	1