Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	248866	1		T1	1		T2	216		T3	760
auto[FlashEraseBank]	276769	1		T4	2		T18	1		T6	809

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	268012	1		T1	1		T2	15		T3	392
auto[FlashOpProgram]	237887	1		T2	192		T3	184		T4	1
auto[FlashOpErase]	15736	1		T2	9		T3	184		T4	1
auto[FlashOpInvalid]	4000	1		T220	200		T151	200		T136	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	268012	1		T1	1		T2	15		T3	392
op[FlashOpProgram]	237887	1		T2	192		T3	184		T4	1
op[FlashOpErase]	15736	1		T2	9		T3	184		T4	1
read_erase_read	524	1		T2	5		T30	2		T19	14
read_prog_read	880	1		T24	2		T40	2		T21	7

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	385081	1		T11	1		T4	4		T18	3
auto[FlashPartInfo]	136811	1		T1	1		T2	216		T3	760
auto[FlashPartInfo1]	929	1		T7	32		T21	2		T61	2
auto[FlashPartInfo2]	2814	1		T7	44		T21	14		T113	1

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	197756	1		T11	1		T4	2		T18	3
auto[FlashPartData]	auto[FlashOpProgram]	179780	1		T4	1		T39	4		T24	3
auto[FlashPartData]	auto[FlashOpErase]	3629	1		T4	1		T19	6		T40	10
auto[FlashPartData]	auto[FlashOpInvalid]	3916	1		T220	200		T151	196		T136	192
auto[FlashPartInfo]	auto[FlashOpRead]	67695	1		T1	1		T2	15		T3	392
auto[FlashPartInfo]	auto[FlashOpProgram]	56970	1		T2	192		T3	184		T30	288
auto[FlashPartInfo]	auto[FlashOpErase]	12074	1		T2	9		T3	184		T30	7
auto[FlashPartInfo]	auto[FlashOpInvalid]	72	1		T151	2		T136	6		T417	2
auto[FlashPartInfo1]	auto[FlashOpRead]	756	1		T7	32		T21	2		T61	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	165	1		T66	1		T138	32		T142	32
auto[FlashPartInfo1]	auto[FlashOpErase]	4	1		T115	1		T144	1		T118	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T144	2		T418	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1805	1		T7	44		T21	6		T113	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	972	1		T21	8		T61	12		T98	1
auto[FlashPartInfo2]	auto[FlashOpErase]	29	1		T151	1		T136	1		T114	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	8	1		T151	2		T136	2		T419	2