Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31107	1		T3	368		T40	8		T42	704
auto[1]	45	1		T24	1		T359	1		T360	25
auto[2]	52	1		T24	1		T113	1		T74	6
auto[3]	265	1		T19	9		T24	1		T25	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7874	1		T3	92		T19	3		T40	2
evic_idx[1]	7869	1		T3	92		T19	3		T24	1
evic_idx[2]	7864	1		T3	92		T19	2		T24	1
evic_idx[3]	7862	1		T3	92		T19	1		T24	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30580	1		T3	368		T19	9		T42	704
evic_op[2]	298	1		T24	3		T25	1		T26	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[1]]	[evic_op[2]]	[auto[1]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7577	1		T3	92		T42	176		T90	31
evic_idx[0]	evic_op[1]	auto[1]	9	1		T360	5		T361	2		T362	2
evic_idx[0]	evic_op[1]	auto[2]	2	1		T363	2		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	65	1		T19	3		T364	3		T365	2
evic_idx[0]	evic_op[2]	auto[0]	60	1		T66	1		T221	4		T238	1
evic_idx[0]	evic_op[2]	auto[1]	1	1		T366	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[2]	4	1		T74	2		T367	2		-	-
evic_idx[0]	evic_op[2]	auto[3]	8	1		T98	1		T150	1		T368	1
evic_idx[1]	evic_op[1]	auto[0]	7577	1		T3	92		T42	176		T90	31
evic_idx[1]	evic_op[1]	auto[1]	14	1		T360	7		T361	2		T362	3
evic_idx[1]	evic_op[1]	auto[2]	2	1		T360	1		T363	1		-	-
evic_idx[1]	evic_op[1]	auto[3]	53	1		T19	3		T364	5		T369	7
evic_idx[1]	evic_op[2]	auto[0]	58	1		T66	1		T221	4		T238	1
evic_idx[1]	evic_op[2]	auto[2]	4	1		T24	1		T74	1		T370	1
evic_idx[1]	evic_op[2]	auto[3]	13	1		T124	1		T125	1		T212	1
evic_idx[2]	evic_op[1]	auto[0]	7577	1		T3	92		T42	176		T90	31
evic_idx[2]	evic_op[1]	auto[1]	10	1		T360	7		T361	2		T363	1
evic_idx[2]	evic_op[1]	auto[2]	2	1		T363	2		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	50	1		T19	2		T364	6		T365	2
evic_idx[2]	evic_op[2]	auto[0]	61	1		T66	1		T221	4		T238	1
evic_idx[2]	evic_op[2]	auto[1]	2	1		T24	1		T371	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	5	1		T113	1		T74	2		T367	1
evic_idx[2]	evic_op[2]	auto[3]	9	1		T26	1		T113	1		T368	1
evic_idx[3]	evic_op[1]	auto[0]	7578	1		T3	92		T42	176		T90	31
evic_idx[3]	evic_op[1]	auto[1]	7	1		T360	6		T361	1		-	-
evic_idx[3]	evic_op[1]	auto[2]	1	1		T363	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	56	1		T19	1		T364	5		T365	2
evic_idx[3]	evic_op[2]	auto[0]	56	1		T66	1		T221	4		T238	1
evic_idx[3]	evic_op[2]	auto[1]	2	1		T359	1		T372	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	4	1		T74	1		T373	2		T374	1
evic_idx[3]	evic_op[2]	auto[3]	11	1		T24	1		T25	1		T122	1