Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	23067	1		T341	2133		T342	2168		T343	2614
rd_lvl[2]	46566	1		T341	897		T344	12896		T83	12517
rd_lvl[3]	11019	1		T341	326		T344	336		T83	408
rd_lvl[4]	18931	1		T345	5497		T341	427		T346	2809
rd_lvl[5]	13599	1		T35	2480		T345	1243		T347	153
rd_lvl[6]	19669	1		T35	2845		T348	2368		T345	21
rd_lvl[7]	9399	1		T348	357		T349	602		T345	42
rd_lvl[8]	22039	1		T350	2996		T349	294		T345	60
rd_lvl[9]	9008	1		T6	681		T7	193		T350	344
rd_lvl[10]	12460	1		T6	1078		T7	105		T33	572
rd_lvl[11]	3663	1		T33	175		T284	261		T351	420
rd_lvl[12]	5186	1		T7	21		T284	215		T352	65
rd_lvl[13]	1526	1		T352	22		T353	242		T354	45
rd_lvl[14]	8524	1		T284	48		T341	217		T355	1236
rd_lvl[15]	5328	1		T32	244		T254	536		T352	1