Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	328613	1		T1	1		T2	2		T3	1
all_pins[1]	328613	1		T1	1		T2	2		T3	1
all_pins[2]	328613	1		T1	1		T2	2		T3	1
all_pins[3]	328613	1		T1	1		T2	2		T3	1
all_pins[4]	328613	1		T1	1		T2	2		T3	1
all_pins[5]	328613	1		T1	1		T2	2		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1630288	1		T1	6		T2	12		T3	6
values[0x1]	341390	1		T6	3518		T7	638		T35	8395
transitions[0x0=>0x1]	304757	1		T6	3518		T7	638		T35	7100
transitions[0x1=>0x0]	304738	1		T6	3518		T7	638		T35	7100

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	328440	1		T1	1		T2	2		T3	1
all_pins[0]	values[0x1]	173	1		T269	2		T270	6		T271	2
all_pins[0]	transitions[0x0=>0x1]	91	1		T269	2		T270	5		T271	1
all_pins[0]	transitions[0x1=>0x0]	70	1		T270	1		T271	2		T335	3
all_pins[1]	values[0x0]	328461	1		T1	1		T2	2		T3	1
all_pins[1]	values[0x1]	152	1		T270	2		T271	3		T335	3
all_pins[1]	transitions[0x0=>0x1]	125	1		T270	2		T271	2		T335	2
all_pins[1]	transitions[0x1=>0x0]	4012	1		T32	308		T254	1173		T375	1195
all_pins[2]	values[0x0]	324574	1		T1	1		T2	2		T3	1
all_pins[2]	values[0x1]	4039	1		T32	308		T254	1173		T375	1195
all_pins[2]	transitions[0x0=>0x1]	50	1		T269	1		T271	2		T335	1
all_pins[2]	transitions[0x1=>0x0]	210416	1		T6	1759		T7	319		T35	5325
all_pins[3]	values[0x0]	114208	1		T1	1		T2	2		T3	1
all_pins[3]	values[0x1]	214405	1		T6	1759		T7	319		T35	5325
all_pins[3]	transitions[0x0=>0x1]	181924	1		T6	1759		T7	319		T35	4030
all_pins[3]	transitions[0x1=>0x0]	90085	1		T6	1759		T7	319		T35	1775
all_pins[4]	values[0x0]	206047	1		T1	1		T2	2		T3	1
all_pins[4]	values[0x1]	122566	1		T6	1759		T7	319		T35	3070
all_pins[4]	transitions[0x0=>0x1]	122546	1		T6	1759		T7	319		T35	3070
all_pins[4]	transitions[0x1=>0x0]	35	1		T270	1		T271	1		T339	1
all_pins[5]	values[0x0]	328558	1		T1	1		T2	2		T3	1
all_pins[5]	values[0x1]	55	1		T270	1		T271	1		T339	1
all_pins[5]	transitions[0x0=>0x1]	21	1		T271	1		T338	2		T340	1
all_pins[5]	transitions[0x1=>0x0]	120	1		T269	2		T270	5		T271	2