| T1075 |
/workspace/coverage/default/14.flash_ctrl_lcmgr_intg.202719518 |
|
|
Jul 19 05:51:57 PM PDT 24 |
Jul 19 05:52:11 PM PDT 24 |
17034800 ps |
| T1076 |
/workspace/coverage/default/15.flash_ctrl_lcmgr_intg.2917605939 |
|
|
Jul 19 05:52:07 PM PDT 24 |
Jul 19 05:52:21 PM PDT 24 |
46426700 ps |
| T111 |
/workspace/coverage/default/3.flash_ctrl_sec_cm.1022628296 |
|
|
Jul 19 05:49:30 PM PDT 24 |
Jul 19 07:11:12 PM PDT 24 |
2886534800 ps |
| T1077 |
/workspace/coverage/default/9.flash_ctrl_ro_serr.3177223200 |
|
|
Jul 19 05:50:45 PM PDT 24 |
Jul 19 05:53:17 PM PDT 24 |
2530566800 ps |
| T1078 |
/workspace/coverage/default/18.flash_ctrl_intr_rd_slow_flash.2957815931 |
|
|
Jul 19 05:52:37 PM PDT 24 |
Jul 19 05:57:14 PM PDT 24 |
24585640700 ps |
| T1079 |
/workspace/coverage/default/9.flash_ctrl_rw_serr.1392259069 |
|
|
Jul 19 05:50:44 PM PDT 24 |
Jul 19 06:00:52 PM PDT 24 |
12200499200 ps |
| T1080 |
/workspace/coverage/default/8.flash_ctrl_alert_test.3247663771 |
|
|
Jul 19 05:50:40 PM PDT 24 |
Jul 19 05:50:55 PM PDT 24 |
132241000 ps |
| T1081 |
/workspace/coverage/default/13.flash_ctrl_rand_ops.1509759006 |
|
|
Jul 19 05:51:33 PM PDT 24 |
Jul 19 06:05:45 PM PDT 24 |
248290700 ps |
| T363 |
/workspace/coverage/default/2.flash_ctrl_re_evict.93729732 |
|
|
Jul 19 05:49:23 PM PDT 24 |
Jul 19 05:49:59 PM PDT 24 |
63814200 ps |
| T1082 |
/workspace/coverage/default/0.flash_ctrl_prog_reset.225842957 |
|
|
Jul 19 05:49:03 PM PDT 24 |
Jul 19 05:51:02 PM PDT 24 |
3075170000 ps |
| T1083 |
/workspace/coverage/default/4.flash_ctrl_re_evict.4101001224 |
|
|
Jul 19 05:49:43 PM PDT 24 |
Jul 19 05:50:19 PM PDT 24 |
87724800 ps |
| T1084 |
/workspace/coverage/default/18.flash_ctrl_mp_regions.1563606410 |
|
|
Jul 19 05:52:34 PM PDT 24 |
Jul 19 05:58:17 PM PDT 24 |
26611751200 ps |
| T1085 |
/workspace/coverage/default/4.flash_ctrl_prog_reset.2605662271 |
|
|
Jul 19 05:49:37 PM PDT 24 |
Jul 19 05:49:54 PM PDT 24 |
21443600 ps |
| T1086 |
/workspace/coverage/default/6.flash_ctrl_connect.3929730044 |
|
|
Jul 19 05:50:15 PM PDT 24 |
Jul 19 05:50:32 PM PDT 24 |
52223400 ps |
| T1087 |
/workspace/coverage/default/2.flash_ctrl_serr_address.2062158809 |
|
|
Jul 19 05:49:25 PM PDT 24 |
Jul 19 05:50:33 PM PDT 24 |
516845800 ps |
| T1088 |
/workspace/coverage/default/5.flash_ctrl_mp_regions.157562849 |
|
|
Jul 19 05:49:48 PM PDT 24 |
Jul 19 05:52:25 PM PDT 24 |
6089750900 ps |
| T1089 |
/workspace/coverage/default/77.flash_ctrl_connect.2644982611 |
|
|
Jul 19 05:55:34 PM PDT 24 |
Jul 19 05:55:48 PM PDT 24 |
18318700 ps |
| T1090 |
/workspace/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2626697415 |
|
|
Jul 19 05:49:13 PM PDT 24 |
Jul 19 05:51:05 PM PDT 24 |
10013021500 ps |
| T1091 |
/workspace/coverage/default/0.flash_ctrl_host_addr_infection.3668110523 |
|
|
Jul 19 05:49:08 PM PDT 24 |
Jul 19 05:49:39 PM PDT 24 |
43972700 ps |
| T1092 |
/workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.1365045329 |
|
|
Jul 19 05:50:30 PM PDT 24 |
Jul 19 05:54:46 PM PDT 24 |
132341118200 ps |
| T1093 |
/workspace/coverage/default/36.flash_ctrl_rw_evict.3414848932 |
|
|
Jul 19 05:54:20 PM PDT 24 |
Jul 19 05:54:51 PM PDT 24 |
41933500 ps |
| T1094 |
/workspace/coverage/default/0.flash_ctrl_otp_reset.4180466638 |
|
|
Jul 19 05:49:00 PM PDT 24 |
Jul 19 05:51:16 PM PDT 24 |
188300100 ps |
| T1095 |
/workspace/coverage/default/0.flash_ctrl_rw.2245366463 |
|
|
Jul 19 05:48:58 PM PDT 24 |
Jul 19 05:58:47 PM PDT 24 |
3517619800 ps |
| T1096 |
/workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.3895390944 |
|
|
Jul 19 05:51:16 PM PDT 24 |
Jul 19 05:56:14 PM PDT 24 |
10024347500 ps |
| T1097 |
/workspace/coverage/default/75.flash_ctrl_otp_reset.3604763358 |
|
|
Jul 19 05:55:33 PM PDT 24 |
Jul 19 05:57:47 PM PDT 24 |
155927000 ps |
| T1098 |
/workspace/coverage/default/18.flash_ctrl_disable.580606278 |
|
|
Jul 19 05:52:44 PM PDT 24 |
Jul 19 05:53:07 PM PDT 24 |
11284700 ps |
| T1099 |
/workspace/coverage/default/29.flash_ctrl_alert_test.351924182 |
|
|
Jul 19 05:53:51 PM PDT 24 |
Jul 19 05:54:06 PM PDT 24 |
28853100 ps |
| T1100 |
/workspace/coverage/default/70.flash_ctrl_connect.1272372109 |
|
|
Jul 19 05:55:22 PM PDT 24 |
Jul 19 05:55:36 PM PDT 24 |
29396700 ps |
| T1101 |
/workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.3266791225 |
|
|
Jul 19 05:48:57 PM PDT 24 |
Jul 19 05:49:24 PM PDT 24 |
24260700 ps |
| T1102 |
/workspace/coverage/default/5.flash_ctrl_fetch_code.750332761 |
|
|
Jul 19 05:49:47 PM PDT 24 |
Jul 19 05:50:15 PM PDT 24 |
446408400 ps |
| T1103 |
/workspace/coverage/default/0.flash_ctrl_ro_derr.2829167532 |
|
|
Jul 19 05:49:05 PM PDT 24 |
Jul 19 05:51:47 PM PDT 24 |
1313670600 ps |
| T1104 |
/workspace/coverage/default/33.flash_ctrl_disable.4288454403 |
|
|
Jul 19 05:54:03 PM PDT 24 |
Jul 19 05:54:26 PM PDT 24 |
15437000 ps |
| T1105 |
/workspace/coverage/default/12.flash_ctrl_sec_info_access.1949447509 |
|
|
Jul 19 05:51:33 PM PDT 24 |
Jul 19 05:52:49 PM PDT 24 |
697298100 ps |
| T1106 |
/workspace/coverage/default/21.flash_ctrl_disable.91988663 |
|
|
Jul 19 05:52:58 PM PDT 24 |
Jul 19 05:53:22 PM PDT 24 |
23009900 ps |
| T1107 |
/workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.1643724713 |
|
|
Jul 19 05:49:13 PM PDT 24 |
Jul 19 05:54:37 PM PDT 24 |
48662397700 ps |
| T1108 |
/workspace/coverage/default/23.flash_ctrl_hw_sec_otp.3837205621 |
|
|
Jul 19 05:53:13 PM PDT 24 |
Jul 19 05:54:08 PM PDT 24 |
7384489400 ps |
| T1109 |
/workspace/coverage/default/24.flash_ctrl_intr_rd.4142839732 |
|
|
Jul 19 05:53:17 PM PDT 24 |
Jul 19 05:55:19 PM PDT 24 |
3985532700 ps |
| T1110 |
/workspace/coverage/default/2.flash_ctrl_sw_op.271360451 |
|
|
Jul 19 05:49:13 PM PDT 24 |
Jul 19 05:49:42 PM PDT 24 |
22553000 ps |
| T1111 |
/workspace/coverage/default/16.flash_ctrl_rand_ops.2856543737 |
|
|
Jul 19 05:52:11 PM PDT 24 |
Jul 19 06:08:38 PM PDT 24 |
3540984300 ps |
| T1112 |
/workspace/coverage/default/8.flash_ctrl_rand_ops.1398233641 |
|
|
Jul 19 05:50:31 PM PDT 24 |
Jul 19 06:14:57 PM PDT 24 |
567567800 ps |
| T1113 |
/workspace/coverage/default/9.flash_ctrl_rand_ops.2909050638 |
|
|
Jul 19 05:50:38 PM PDT 24 |
Jul 19 05:56:32 PM PDT 24 |
64107000 ps |
| T1114 |
/workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.3363610860 |
|
|
Jul 19 05:50:26 PM PDT 24 |
Jul 19 05:50:58 PM PDT 24 |
61870400 ps |
| T1115 |
/workspace/coverage/default/24.flash_ctrl_sec_info_access.2971081802 |
|
|
Jul 19 05:53:23 PM PDT 24 |
Jul 19 05:54:29 PM PDT 24 |
2730003000 ps |
| T1116 |
/workspace/coverage/default/6.flash_ctrl_hw_sec_otp.4061143198 |
|
|
Jul 19 05:49:59 PM PDT 24 |
Jul 19 05:51:17 PM PDT 24 |
1778808700 ps |
| T101 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3773017826 |
|
|
Jul 19 04:33:32 PM PDT 24 |
Jul 19 04:33:59 PM PDT 24 |
54563500 ps |
| T1117 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1438326672 |
|
|
Jul 19 04:33:24 PM PDT 24 |
Jul 19 04:33:46 PM PDT 24 |
30747400 ps |
| T1118 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.4247808165 |
|
|
Jul 19 04:33:57 PM PDT 24 |
Jul 19 04:34:18 PM PDT 24 |
13352300 ps |
| T63 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3205250264 |
|
|
Jul 19 04:33:25 PM PDT 24 |
Jul 19 04:33:47 PM PDT 24 |
81017100 ps |
| T64 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3593588983 |
|
|
Jul 19 04:33:52 PM PDT 24 |
Jul 19 04:34:12 PM PDT 24 |
86328200 ps |
| T1119 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.3943333153 |
|
|
Jul 19 04:33:31 PM PDT 24 |
Jul 19 04:33:52 PM PDT 24 |
24602100 ps |
| T269 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2950309689 |
|
|
Jul 19 04:33:58 PM PDT 24 |
Jul 19 04:34:17 PM PDT 24 |
29688300 ps |
| T104 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.577085347 |
|
|
Jul 19 04:33:46 PM PDT 24 |
Jul 19 04:34:03 PM PDT 24 |
116720300 ps |
| T270 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.3689495349 |
|
|
Jul 19 04:33:50 PM PDT 24 |
Jul 19 04:34:06 PM PDT 24 |
60229500 ps |
| T65 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3078606507 |
|
|
Jul 19 04:33:54 PM PDT 24 |
Jul 19 04:34:15 PM PDT 24 |
217179700 ps |
| T271 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2996464449 |
|
|
Jul 19 04:33:59 PM PDT 24 |
Jul 19 04:34:17 PM PDT 24 |
26576100 ps |
| T261 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3693081205 |
|
|
Jul 19 04:33:54 PM PDT 24 |
Jul 19 04:34:31 PM PDT 24 |
247278900 ps |
| T105 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3554137819 |
|
|
Jul 19 04:33:29 PM PDT 24 |
Jul 19 04:34:24 PM PDT 24 |
94278600 ps |
| T102 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3778668982 |
|
|
Jul 19 04:33:16 PM PDT 24 |
Jul 19 04:33:44 PM PDT 24 |
156423000 ps |
| T103 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3206001819 |
|
|
Jul 19 04:33:42 PM PDT 24 |
Jul 19 04:34:04 PM PDT 24 |
46309100 ps |
| T335 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.2199106429 |
|
|
Jul 19 04:33:53 PM PDT 24 |
Jul 19 04:34:10 PM PDT 24 |
16837600 ps |
| T224 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1600593923 |
|
|
Jul 19 04:33:32 PM PDT 24 |
Jul 19 04:48:42 PM PDT 24 |
730660200 ps |
| T263 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.226286986 |
|
|
Jul 19 04:33:26 PM PDT 24 |
Jul 19 04:33:53 PM PDT 24 |
216580000 ps |
| T1120 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2331872 |
|
|
Jul 19 04:33:23 PM PDT 24 |
Jul 19 04:33:45 PM PDT 24 |
109738700 ps |
| T339 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.3556511091 |
|
|
Jul 19 04:33:47 PM PDT 24 |
Jul 19 04:34:02 PM PDT 24 |
21489600 ps |
| T1121 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.4006759389 |
|
|
Jul 19 04:33:20 PM PDT 24 |
Jul 19 04:33:44 PM PDT 24 |
20656100 ps |
| T1122 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2402518511 |
|
|
Jul 19 04:33:30 PM PDT 24 |
Jul 19 04:33:52 PM PDT 24 |
59948700 ps |
| T1123 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3783963371 |
|
|
Jul 19 04:33:32 PM PDT 24 |
Jul 19 04:33:53 PM PDT 24 |
44830700 ps |
| T336 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.1474054032 |
|
|
Jul 19 04:34:01 PM PDT 24 |
Jul 19 04:34:22 PM PDT 24 |
26835800 ps |
| T337 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.1708939782 |
|
|
Jul 19 04:33:56 PM PDT 24 |
Jul 19 04:34:14 PM PDT 24 |
47834100 ps |
| T338 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.3681867045 |
|
|
Jul 19 04:33:54 PM PDT 24 |
Jul 19 04:34:12 PM PDT 24 |
43648100 ps |
| T234 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.710555235 |
|
|
Jul 19 04:33:29 PM PDT 24 |
Jul 19 04:33:53 PM PDT 24 |
93180700 ps |
| T334 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1948674007 |
|
|
Jul 19 04:33:54 PM PDT 24 |
Jul 19 04:34:14 PM PDT 24 |
32296300 ps |
| T1124 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1774971118 |
|
|
Jul 19 04:33:49 PM PDT 24 |
Jul 19 04:34:04 PM PDT 24 |
31512500 ps |
| T340 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.3693685799 |
|
|
Jul 19 04:33:58 PM PDT 24 |
Jul 19 04:34:16 PM PDT 24 |
47374300 ps |
| T225 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.41693124 |
|
|
Jul 19 04:33:53 PM PDT 24 |
Jul 19 04:34:13 PM PDT 24 |
86035200 ps |
| T1125 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.2271883684 |
|
|
Jul 19 04:33:58 PM PDT 24 |
Jul 19 04:34:17 PM PDT 24 |
89752400 ps |
| T235 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.904538953 |
|
|
Jul 19 04:33:24 PM PDT 24 |
Jul 19 04:33:52 PM PDT 24 |
113990800 ps |
| T262 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3363767191 |
|
|
Jul 19 04:34:00 PM PDT 24 |
Jul 19 04:34:24 PM PDT 24 |
39385700 ps |
| T1126 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.4210971684 |
|
|
Jul 19 04:33:57 PM PDT 24 |
Jul 19 04:34:15 PM PDT 24 |
61421900 ps |
| T1127 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.484834989 |
|
|
Jul 19 04:33:51 PM PDT 24 |
Jul 19 04:34:07 PM PDT 24 |
14742200 ps |
| T1128 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1079922497 |
|
|
Jul 19 04:33:53 PM PDT 24 |
Jul 19 04:34:09 PM PDT 24 |
17786900 ps |
| T264 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.4007856151 |
|
|
Jul 19 04:33:31 PM PDT 24 |
Jul 19 04:33:57 PM PDT 24 |
117754800 ps |
| T239 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3942770260 |
|
|
Jul 19 04:33:19 PM PDT 24 |
Jul 19 04:33:40 PM PDT 24 |
28690500 ps |
| T1129 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.943976278 |
|
|
Jul 19 04:33:37 PM PDT 24 |
Jul 19 04:33:57 PM PDT 24 |
14855700 ps |
| T1130 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2524972214 |
|
|
Jul 19 04:33:57 PM PDT 24 |
Jul 19 04:34:15 PM PDT 24 |
27584700 ps |
| T1131 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2851242511 |
|
|
Jul 19 04:33:29 PM PDT 24 |
Jul 19 04:33:53 PM PDT 24 |
14361900 ps |
| T1132 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.97292846 |
|
|
Jul 19 04:33:48 PM PDT 24 |
Jul 19 04:34:03 PM PDT 24 |
12993600 ps |
| T237 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2173794854 |
|
|
Jul 19 04:33:55 PM PDT 24 |
Jul 19 04:41:39 PM PDT 24 |
1642698400 ps |
| T236 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.2916948286 |
|
|
Jul 19 04:33:22 PM PDT 24 |
Jul 19 04:33:49 PM PDT 24 |
374117200 ps |
| T281 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1994098252 |
|
|
Jul 19 04:33:29 PM PDT 24 |
Jul 19 04:33:56 PM PDT 24 |
40536200 ps |
| T1133 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.177238167 |
|
|
Jul 19 04:33:55 PM PDT 24 |
Jul 19 04:34:35 PM PDT 24 |
936582800 ps |
| T1134 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.4029219474 |
|
|
Jul 19 04:33:30 PM PDT 24 |
Jul 19 04:33:51 PM PDT 24 |
27959700 ps |
| T1135 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3976970685 |
|
|
Jul 19 04:33:38 PM PDT 24 |
Jul 19 04:33:55 PM PDT 24 |
36341300 ps |
| T308 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.187357344 |
|
|
Jul 19 04:33:33 PM PDT 24 |
Jul 19 04:33:56 PM PDT 24 |
67385600 ps |
| T1136 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.3213387779 |
|
|
Jul 19 04:33:29 PM PDT 24 |
Jul 19 04:33:51 PM PDT 24 |
25167200 ps |
| T1137 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.341172225 |
|
|
Jul 19 04:33:30 PM PDT 24 |
Jul 19 04:33:54 PM PDT 24 |
36412900 ps |
| T387 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2259871837 |
|
|
Jul 19 04:33:44 PM PDT 24 |
Jul 19 04:34:03 PM PDT 24 |
96162300 ps |
| T421 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1689146298 |
|
|
Jul 19 04:33:27 PM PDT 24 |
Jul 19 04:34:07 PM PDT 24 |
229108200 ps |
| T259 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1633538639 |
|
|
Jul 19 04:33:31 PM PDT 24 |
Jul 19 04:41:14 PM PDT 24 |
596896600 ps |
| T309 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2347507420 |
|
|
Jul 19 04:33:57 PM PDT 24 |
Jul 19 04:34:18 PM PDT 24 |
201747400 ps |
| T310 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2628571486 |
|
|
Jul 19 04:33:32 PM PDT 24 |
Jul 19 04:34:23 PM PDT 24 |
923716500 ps |
| T1138 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1224770545 |
|
|
Jul 19 04:33:58 PM PDT 24 |
Jul 19 04:34:15 PM PDT 24 |
34498400 ps |
| T1139 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.988458001 |
|
|
Jul 19 04:33:51 PM PDT 24 |
Jul 19 04:34:10 PM PDT 24 |
13752800 ps |
| T1140 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2345953108 |
|
|
Jul 19 04:34:01 PM PDT 24 |
Jul 19 04:34:21 PM PDT 24 |
143377500 ps |
| T1141 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.1525962634 |
|
|
Jul 19 04:33:46 PM PDT 24 |
Jul 19 04:34:01 PM PDT 24 |
17665900 ps |
| T1142 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1540634608 |
|
|
Jul 19 04:33:28 PM PDT 24 |
Jul 19 04:34:23 PM PDT 24 |
25214000 ps |
| T1143 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3082883801 |
|
|
Jul 19 04:33:26 PM PDT 24 |
Jul 19 04:33:51 PM PDT 24 |
172250600 ps |
| T267 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1978016862 |
|
|
Jul 19 04:33:45 PM PDT 24 |
Jul 19 04:34:02 PM PDT 24 |
585323600 ps |
| T1144 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3315232053 |
|
|
Jul 19 04:33:47 PM PDT 24 |
Jul 19 04:34:04 PM PDT 24 |
59498800 ps |
| T1145 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3860750876 |
|
|
Jul 19 04:33:48 PM PDT 24 |
Jul 19 04:34:07 PM PDT 24 |
36843300 ps |
| T276 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2379226274 |
|
|
Jul 19 04:33:48 PM PDT 24 |
Jul 19 04:41:33 PM PDT 24 |
1713983300 ps |
| T1146 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3866623171 |
|
|
Jul 19 04:33:54 PM PDT 24 |
Jul 19 04:34:13 PM PDT 24 |
103564400 ps |
| T1147 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3846683253 |
|
|
Jul 19 04:33:35 PM PDT 24 |
Jul 19 04:34:15 PM PDT 24 |
132765000 ps |
| T1148 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3465865552 |
|
|
Jul 19 04:33:53 PM PDT 24 |
Jul 19 04:34:14 PM PDT 24 |
324336900 ps |
| T265 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1231529774 |
|
|
Jul 19 04:33:31 PM PDT 24 |
Jul 19 04:33:56 PM PDT 24 |
300424100 ps |
| T376 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.978574851 |
|
|
Jul 19 04:33:24 PM PDT 24 |
Jul 19 04:39:56 PM PDT 24 |
1435837500 ps |
| T311 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3851030399 |
|
|
Jul 19 04:33:53 PM PDT 24 |
Jul 19 04:46:36 PM PDT 24 |
1835645000 ps |
| T312 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3052946599 |
|
|
Jul 19 04:33:54 PM PDT 24 |
Jul 19 04:34:17 PM PDT 24 |
197400000 ps |
| T1149 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2925549583 |
|
|
Jul 19 04:33:25 PM PDT 24 |
Jul 19 04:34:05 PM PDT 24 |
31201800 ps |
| T272 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.377850516 |
|
|
Jul 19 04:33:55 PM PDT 24 |
Jul 19 04:34:18 PM PDT 24 |
34478500 ps |
| T1150 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1580388804 |
|
|
Jul 19 04:33:47 PM PDT 24 |
Jul 19 04:34:02 PM PDT 24 |
18802600 ps |
| T1151 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.267429948 |
|
|
Jul 19 04:33:28 PM PDT 24 |
Jul 19 04:33:52 PM PDT 24 |
84734000 ps |
| T1152 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.931928568 |
|
|
Jul 19 04:34:03 PM PDT 24 |
Jul 19 04:34:23 PM PDT 24 |
66861300 ps |
| T1153 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1148979615 |
|
|
Jul 19 04:33:16 PM PDT 24 |
Jul 19 04:33:56 PM PDT 24 |
217645800 ps |
| T1154 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3267778144 |
|
|
Jul 19 04:33:29 PM PDT 24 |
Jul 19 04:33:50 PM PDT 24 |
12777300 ps |
| T1155 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2448454694 |
|
|
Jul 19 04:33:55 PM PDT 24 |
Jul 19 04:34:14 PM PDT 24 |
51389900 ps |
| T1156 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.180424390 |
|
|
Jul 19 04:33:54 PM PDT 24 |
Jul 19 04:34:13 PM PDT 24 |
16890300 ps |
| T1157 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.1472691286 |
|
|
Jul 19 04:33:30 PM PDT 24 |
Jul 19 04:34:11 PM PDT 24 |
231833700 ps |
| T381 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.217249070 |
|
|
Jul 19 04:33:35 PM PDT 24 |
Jul 19 04:48:42 PM PDT 24 |
333022000 ps |
| T1158 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3180797270 |
|
|
Jul 19 04:33:52 PM PDT 24 |
Jul 19 04:34:10 PM PDT 24 |
94459600 ps |
| T1159 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1381674652 |
|
|
Jul 19 04:33:26 PM PDT 24 |
Jul 19 04:33:50 PM PDT 24 |
27083600 ps |
| T240 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.500243772 |
|
|
Jul 19 04:33:25 PM PDT 24 |
Jul 19 04:33:47 PM PDT 24 |
27675400 ps |
| T1160 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.711651318 |
|
|
Jul 19 04:33:25 PM PDT 24 |
Jul 19 04:33:47 PM PDT 24 |
96492100 ps |
| T1161 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.4217302235 |
|
|
Jul 19 04:34:03 PM PDT 24 |
Jul 19 04:34:27 PM PDT 24 |
43539400 ps |
| T1162 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3037537937 |
|
|
Jul 19 04:33:41 PM PDT 24 |
Jul 19 04:33:58 PM PDT 24 |
26911400 ps |
| T1163 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.48017888 |
|
|
Jul 19 04:33:50 PM PDT 24 |
Jul 19 04:34:04 PM PDT 24 |
16283800 ps |
| T1164 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.881012408 |
|
|
Jul 19 04:33:41 PM PDT 24 |
Jul 19 04:33:58 PM PDT 24 |
56010400 ps |
| T1165 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2153186125 |
|
|
Jul 19 04:33:30 PM PDT 24 |
Jul 19 04:33:52 PM PDT 24 |
34674400 ps |
| T313 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3128403441 |
|
|
Jul 19 04:33:52 PM PDT 24 |
Jul 19 04:34:13 PM PDT 24 |
262709200 ps |
| T314 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2060745236 |
|
|
Jul 19 04:33:26 PM PDT 24 |
Jul 19 04:33:53 PM PDT 24 |
375014300 ps |
| T1166 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.511664096 |
|
|
Jul 19 04:33:34 PM PDT 24 |
Jul 19 04:33:57 PM PDT 24 |
57146900 ps |
| T1167 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1349433308 |
|
|
Jul 19 04:33:53 PM PDT 24 |
Jul 19 04:34:10 PM PDT 24 |
17058300 ps |
| T315 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2820415730 |
|
|
Jul 19 04:33:15 PM PDT 24 |
Jul 19 04:33:55 PM PDT 24 |
59448700 ps |
| T1168 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.358763956 |
|
|
Jul 19 04:33:57 PM PDT 24 |
Jul 19 04:34:16 PM PDT 24 |
50019200 ps |
| T241 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3477316415 |
|
|
Jul 19 04:33:21 PM PDT 24 |
Jul 19 04:33:44 PM PDT 24 |
32829000 ps |
| T1169 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.684247374 |
|
|
Jul 19 04:33:30 PM PDT 24 |
Jul 19 04:34:08 PM PDT 24 |
164136000 ps |
| T316 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1460013509 |
|
|
Jul 19 04:33:55 PM PDT 24 |
Jul 19 04:34:17 PM PDT 24 |
266185100 ps |
| T1170 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2459225049 |
|
|
Jul 19 04:34:03 PM PDT 24 |
Jul 19 04:34:24 PM PDT 24 |
19017200 ps |
| T279 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1334256326 |
|
|
Jul 19 04:33:34 PM PDT 24 |
Jul 19 04:33:57 PM PDT 24 |
91139200 ps |
| T1171 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.341140121 |
|
|
Jul 19 04:33:29 PM PDT 24 |
Jul 19 04:34:08 PM PDT 24 |
145730700 ps |
| T1172 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2798964509 |
|
|
Jul 19 04:33:23 PM PDT 24 |
Jul 19 04:33:51 PM PDT 24 |
27216200 ps |
| T1173 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.370092697 |
|
|
Jul 19 04:33:27 PM PDT 24 |
Jul 19 04:34:51 PM PDT 24 |
3280272300 ps |
| T266 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3934896218 |
|
|
Jul 19 04:33:50 PM PDT 24 |
Jul 19 04:34:10 PM PDT 24 |
115243600 ps |
| T1174 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1654656030 |
|
|
Jul 19 04:33:33 PM PDT 24 |
Jul 19 04:33:54 PM PDT 24 |
16460800 ps |
| T1175 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2103960645 |
|
|
Jul 19 04:33:47 PM PDT 24 |
Jul 19 04:34:05 PM PDT 24 |
14324400 ps |
| T1176 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.732471364 |
|
|
Jul 19 04:33:26 PM PDT 24 |
Jul 19 04:33:53 PM PDT 24 |
51018700 ps |
| T1177 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.312917248 |
|
|
Jul 19 04:33:33 PM PDT 24 |
Jul 19 04:33:56 PM PDT 24 |
119811300 ps |
| T1178 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2674233401 |
|
|
Jul 19 04:33:51 PM PDT 24 |
Jul 19 04:34:11 PM PDT 24 |
56538400 ps |
| T1179 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.723803965 |
|
|
Jul 19 04:33:58 PM PDT 24 |
Jul 19 04:34:16 PM PDT 24 |
35398500 ps |
| T1180 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.653641834 |
|
|
Jul 19 04:33:23 PM PDT 24 |
Jul 19 04:33:48 PM PDT 24 |
14783500 ps |
| T1181 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2140748516 |
|
|
Jul 19 04:33:52 PM PDT 24 |
Jul 19 04:34:11 PM PDT 24 |
21747600 ps |
| T1182 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.3568406515 |
|
|
Jul 19 04:33:30 PM PDT 24 |
Jul 19 04:33:56 PM PDT 24 |
46207100 ps |
| T1183 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.260621496 |
|
|
Jul 19 04:33:30 PM PDT 24 |
Jul 19 04:33:52 PM PDT 24 |
17687000 ps |
| T1184 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2358188825 |
|
|
Jul 19 04:33:55 PM PDT 24 |
Jul 19 04:34:15 PM PDT 24 |
33257000 ps |
| T1185 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1500463767 |
|
|
Jul 19 04:33:21 PM PDT 24 |
Jul 19 04:33:43 PM PDT 24 |
22290600 ps |
| T1186 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1371816810 |
|
|
Jul 19 04:33:35 PM PDT 24 |
Jul 19 04:33:56 PM PDT 24 |
124560600 ps |
| T1187 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.676724554 |
|
|
Jul 19 04:33:56 PM PDT 24 |
Jul 19 04:34:14 PM PDT 24 |
18232500 ps |
| T1188 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1791089573 |
|
|
Jul 19 04:33:47 PM PDT 24 |
Jul 19 04:34:02 PM PDT 24 |
25604400 ps |
| T382 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.1509988481 |
|
|
Jul 19 04:33:47 PM PDT 24 |
Jul 19 04:41:32 PM PDT 24 |
653077300 ps |
| T1189 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.1816225227 |
|
|
Jul 19 04:33:56 PM PDT 24 |
Jul 19 04:34:14 PM PDT 24 |
42249700 ps |
| T1190 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.972535945 |
|
|
Jul 19 04:33:56 PM PDT 24 |
Jul 19 04:34:18 PM PDT 24 |
92005400 ps |
| T242 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1945580025 |
|
|
Jul 19 04:33:31 PM PDT 24 |
Jul 19 04:33:52 PM PDT 24 |
28292700 ps |
| T1191 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.649812460 |
|
|
Jul 19 04:33:46 PM PDT 24 |
Jul 19 04:34:00 PM PDT 24 |
32079100 ps |
| T1192 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3969500656 |
|
|
Jul 19 04:33:27 PM PDT 24 |
Jul 19 04:33:51 PM PDT 24 |
30205600 ps |
| T1193 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.460248685 |
|
|
Jul 19 04:33:57 PM PDT 24 |
Jul 19 04:34:15 PM PDT 24 |
25581000 ps |
| T1194 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3420127235 |
|
|
Jul 19 04:34:02 PM PDT 24 |
Jul 19 04:34:26 PM PDT 24 |
107139000 ps |
| T1195 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.3472343439 |
|
|
Jul 19 04:33:56 PM PDT 24 |
Jul 19 04:34:18 PM PDT 24 |
80993500 ps |
| T1196 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3819208466 |
|
|
Jul 19 04:33:56 PM PDT 24 |
Jul 19 04:34:17 PM PDT 24 |
17258600 ps |
| T379 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2014617372 |
|
|
Jul 19 04:33:42 PM PDT 24 |
Jul 19 04:48:46 PM PDT 24 |
2518118200 ps |
| T1197 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.630904331 |
|
|
Jul 19 04:33:32 PM PDT 24 |
Jul 19 04:33:55 PM PDT 24 |
74769500 ps |
| T274 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.893940012 |
|
|
Jul 19 04:33:29 PM PDT 24 |
Jul 19 04:48:37 PM PDT 24 |
1998667900 ps |
| T385 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2073452777 |
|
|
Jul 19 04:33:29 PM PDT 24 |
Jul 19 04:48:56 PM PDT 24 |
2860364800 ps |
| T268 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.913449552 |
|
|
Jul 19 04:33:28 PM PDT 24 |
Jul 19 04:33:57 PM PDT 24 |
229230200 ps |
| T1198 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.4224187515 |
|
|
Jul 19 04:33:33 PM PDT 24 |
Jul 19 04:33:56 PM PDT 24 |
42336700 ps |
| T273 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1148375421 |
|
|
Jul 19 04:33:35 PM PDT 24 |
Jul 19 04:33:57 PM PDT 24 |
40570200 ps |
| T1199 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1604212191 |
|
|
Jul 19 04:33:58 PM PDT 24 |
Jul 19 04:34:16 PM PDT 24 |
47554400 ps |
| T1200 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.1179757128 |
|
|
Jul 19 04:33:24 PM PDT 24 |
Jul 19 04:33:49 PM PDT 24 |
43550600 ps |
| T1201 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2814790473 |
|
|
Jul 19 04:33:50 PM PDT 24 |
Jul 19 04:34:35 PM PDT 24 |
4978143900 ps |
| T1202 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2486036085 |
|
|
Jul 19 04:33:45 PM PDT 24 |
Jul 19 04:34:00 PM PDT 24 |
35873300 ps |
| T275 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.3210484877 |
|
|
Jul 19 04:33:32 PM PDT 24 |
Jul 19 04:33:58 PM PDT 24 |
106322300 ps |
| T380 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3548786220 |
|
|
Jul 19 04:33:56 PM PDT 24 |
Jul 19 04:41:39 PM PDT 24 |
355677700 ps |
| T317 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.2259588313 |
|
|
Jul 19 04:34:00 PM PDT 24 |
Jul 19 04:34:23 PM PDT 24 |
354302000 ps |
| T1203 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3853223758 |
|
|
Jul 19 04:33:53 PM PDT 24 |
Jul 19 04:34:12 PM PDT 24 |
12395500 ps |
| T243 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1433829898 |
|
|
Jul 19 04:33:25 PM PDT 24 |
Jul 19 04:33:48 PM PDT 24 |
32118600 ps |
| T278 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3591158808 |
|
|
Jul 19 04:33:23 PM PDT 24 |
Jul 19 04:33:50 PM PDT 24 |
57874300 ps |
| T318 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1021755248 |
|
|
Jul 19 04:33:52 PM PDT 24 |
Jul 19 04:34:12 PM PDT 24 |
194491500 ps |
| T1204 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.1985382251 |
|
|
Jul 19 04:34:00 PM PDT 24 |
Jul 19 04:34:19 PM PDT 24 |
32152500 ps |
| T1205 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.783192709 |
|
|
Jul 19 04:33:32 PM PDT 24 |
Jul 19 04:34:14 PM PDT 24 |
2772825300 ps |
| T1206 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.2877372707 |
|
|
Jul 19 04:33:53 PM PDT 24 |
Jul 19 04:34:15 PM PDT 24 |
131008500 ps |
| T383 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1086601629 |
|
|
Jul 19 04:33:24 PM PDT 24 |
Jul 19 04:46:13 PM PDT 24 |
4970888000 ps |
| T1207 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.151103335 |
|
|
Jul 19 04:33:32 PM PDT 24 |
Jul 19 04:33:56 PM PDT 24 |
88677100 ps |
| T1208 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.4013219585 |
|
|
Jul 19 04:34:03 PM PDT 24 |
Jul 19 04:41:49 PM PDT 24 |
174305000 ps |
| T1209 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.45653429 |
|
|
Jul 19 04:33:38 PM PDT 24 |
Jul 19 04:33:59 PM PDT 24 |
18938100 ps |
| T1210 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.780562386 |
|
|
Jul 19 04:33:59 PM PDT 24 |
Jul 19 04:34:20 PM PDT 24 |
12462900 ps |
| T1211 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.1942111122 |
|
|
Jul 19 04:33:52 PM PDT 24 |
Jul 19 04:34:09 PM PDT 24 |
17016600 ps |
| T1212 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.153940645 |
|
|
Jul 19 04:33:46 PM PDT 24 |
Jul 19 04:34:02 PM PDT 24 |
160194000 ps |
| T377 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.46636252 |
|
|
Jul 19 04:33:32 PM PDT 24 |
Jul 19 04:41:18 PM PDT 24 |
183633600 ps |
| T1213 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3709555450 |
|
|
Jul 19 04:33:53 PM PDT 24 |
Jul 19 04:34:11 PM PDT 24 |
38488900 ps |
| T1214 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2318504989 |
|
|
Jul 19 04:33:51 PM PDT 24 |
Jul 19 04:34:07 PM PDT 24 |
40552400 ps |
| T1215 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2351314172 |
|
|
Jul 19 04:33:50 PM PDT 24 |
Jul 19 04:34:09 PM PDT 24 |
105618400 ps |
| T1216 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2852701910 |
|
|
Jul 19 04:33:28 PM PDT 24 |
Jul 19 04:33:53 PM PDT 24 |
33139500 ps |
| T1217 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3352405893 |
|
|
Jul 19 04:33:43 PM PDT 24 |
Jul 19 04:48:52 PM PDT 24 |
3615657100 ps |
| T1218 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2405177590 |
|
|
Jul 19 04:33:37 PM PDT 24 |
Jul 19 04:34:01 PM PDT 24 |
20707000 ps |
| T1219 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1339053706 |
|
|
Jul 19 04:33:31 PM PDT 24 |
Jul 19 04:33:55 PM PDT 24 |
71952800 ps |
| T1220 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.1139061780 |
|
|
Jul 19 04:33:50 PM PDT 24 |
Jul 19 04:34:05 PM PDT 24 |
79440900 ps |
| T378 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3677511217 |
|
|
Jul 19 04:33:30 PM PDT 24 |
Jul 19 04:46:12 PM PDT 24 |
392406100 ps |
| T1221 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3943267783 |
|
|
Jul 19 04:33:53 PM PDT 24 |
Jul 19 04:34:11 PM PDT 24 |
17905800 ps |
| T1222 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1023050450 |
|
|
Jul 19 04:33:35 PM PDT 24 |
Jul 19 04:33:54 PM PDT 24 |
62891900 ps |
| T1223 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2633366651 |
|
|
Jul 19 04:33:25 PM PDT 24 |
Jul 19 04:33:51 PM PDT 24 |
100002000 ps |
| T280 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.772853802 |
|
|
Jul 19 04:33:20 PM PDT 24 |
Jul 19 04:33:45 PM PDT 24 |
38181700 ps |
| T1224 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2442715424 |
|
|
Jul 19 04:33:47 PM PDT 24 |
Jul 19 04:34:02 PM PDT 24 |
44481600 ps |
| T1225 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3778960300 |
|
|
Jul 19 04:33:23 PM PDT 24 |
Jul 19 04:33:47 PM PDT 24 |
32111100 ps |
| T277 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1630348466 |
|
|
Jul 19 04:33:36 PM PDT 24 |
Jul 19 04:34:00 PM PDT 24 |
112579400 ps |
| T1226 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.2224845663 |
|
|
Jul 19 04:33:31 PM PDT 24 |
Jul 19 04:33:56 PM PDT 24 |
123968300 ps |
| T1227 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3629529 |
|
|
Jul 19 04:33:23 PM PDT 24 |
Jul 19 04:33:51 PM PDT 24 |
109487300 ps |
| T1228 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.775684952 |
|
|
Jul 19 04:33:51 PM PDT 24 |
Jul 19 04:34:49 PM PDT 24 |
1269418000 ps |
| T1229 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2046150579 |
|
|
Jul 19 04:33:20 PM PDT 24 |
Jul 19 04:33:44 PM PDT 24 |
247208600 ps |
| T1230 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1667298922 |
|
|
Jul 19 04:33:25 PM PDT 24 |
Jul 19 04:33:51 PM PDT 24 |
356122000 ps |
| T1231 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.4246219738 |
|
|
Jul 19 04:33:26 PM PDT 24 |
Jul 19 04:33:50 PM PDT 24 |
80928300 ps |
| T1232 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.3432336368 |
|
|
Jul 19 04:34:01 PM PDT 24 |
Jul 19 04:34:21 PM PDT 24 |
57610900 ps |
| T319 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.692853215 |
|
|
Jul 19 04:33:36 PM PDT 24 |
Jul 19 04:33:58 PM PDT 24 |
229786800 ps |
| T1233 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2763944201 |
|
|
Jul 19 04:34:00 PM PDT 24 |
Jul 19 04:34:25 PM PDT 24 |
306006800 ps |
| T384 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.27642197 |
|
|
Jul 19 04:33:43 PM PDT 24 |
Jul 19 04:46:26 PM PDT 24 |
683940200 ps |
| T1234 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2173403492 |
|
|
Jul 19 04:33:34 PM PDT 24 |
Jul 19 04:33:56 PM PDT 24 |
24124200 ps |
| T1235 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.548526141 |
|
|
Jul 19 04:33:57 PM PDT 24 |
Jul 19 04:34:18 PM PDT 24 |
627079900 ps |
| T1236 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2603725149 |
|
|
Jul 19 04:33:15 PM PDT 24 |
Jul 19 04:33:37 PM PDT 24 |
54548200 ps |
| T1237 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.76239901 |
|
|
Jul 19 04:33:46 PM PDT 24 |
Jul 19 04:34:01 PM PDT 24 |
17978300 ps |
| T1238 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.2717028623 |
|
|
Jul 19 04:33:15 PM PDT 24 |
Jul 19 04:34:32 PM PDT 24 |
3361216800 ps |
| T1239 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.582830307 |
|
|
Jul 19 04:33:30 PM PDT 24 |
Jul 19 04:34:48 PM PDT 24 |
2841353500 ps |
| T1240 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1587809780 |
|
|
Jul 19 04:33:26 PM PDT 24 |
Jul 19 04:33:55 PM PDT 24 |
453897400 ps |
| T1241 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.166681870 |
|
|
Jul 19 04:33:59 PM PDT 24 |
Jul 19 04:34:21 PM PDT 24 |
73192300 ps |
| T1242 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.215930777 |
|
|
Jul 19 04:34:00 PM PDT 24 |
Jul 19 04:34:20 PM PDT 24 |
25479800 ps |
| T1243 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2292961049 |
|
|
Jul 19 04:33:36 PM PDT 24 |
Jul 19 04:33:59 PM PDT 24 |
67022300 ps |
| T1244 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3973713520 |
|
|
Jul 19 04:34:07 PM PDT 24 |
Jul 19 04:34:32 PM PDT 24 |
26537000 ps |
| T1245 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.1863514744 |
|
|
Jul 19 04:33:46 PM PDT 24 |
Jul 19 04:34:02 PM PDT 24 |
60344000 ps |
| T1246 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2289816377 |
|
|
Jul 19 04:33:35 PM PDT 24 |
Jul 19 04:33:56 PM PDT 24 |
208324600 ps |
| T1247 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.517804020 |
|
|
Jul 19 04:34:08 PM PDT 24 |
Jul 19 04:34:34 PM PDT 24 |
19223200 ps |
| T1248 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3980629816 |
|
|
Jul 19 04:34:03 PM PDT 24 |
Jul 19 04:34:29 PM PDT 24 |
220285400 ps |
| T1249 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2864170248 |
|
|
Jul 19 04:33:26 PM PDT 24 |
Jul 19 04:33:52 PM PDT 24 |
36941700 ps |
| T1250 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.160485315 |
|
|
Jul 19 04:33:34 PM PDT 24 |
Jul 19 04:33:56 PM PDT 24 |
19739200 ps |