Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	270984	1		T1	1		T2	1		T3	1
all_values[1]	270984	1		T1	1		T2	1		T3	1
all_values[2]	270984	1		T1	1		T2	1		T3	1
all_values[3]	270984	1		T1	1		T2	1		T3	1
all_values[4]	270984	1		T1	1		T2	1		T3	1
all_values[5]	270984	1		T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	548065	1		T1	6		T2	6		T3	6
auto[1]	1077839	1		T6	6868		T7	13960		T8	26336

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	796698	1		T1	4		T2	4		T3	4
auto[1]	829206	1		T1	2		T2	2		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	270822	1		T1	1		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	162	1		T255	4		T256	2		T257	5
all_values[1]	auto[0]	auto[1]	270839	1		T1	1		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	145	1		T255	3		T256	3		T257	6
all_values[2]	auto[0]	auto[0]	1552	1		T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	55	1		T255	1		T257	1		T319	1
all_values[2]	auto[1]	auto[0]	269331	1		T6	1717		T7	3490		T8	6584
all_values[2]	auto[1]	auto[1]	46	1		T255	3		T256	1		T257	1
all_values[3]	auto[0]	auto[0]	1518	1		T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	51	1		T255	2		T256	2		T319	1
all_values[3]	auto[1]	auto[0]	79148	1		T6	291		T7	1745		T8	1646
all_values[3]	auto[1]	auto[1]	190267	1		T6	1426		T7	1745		T8	4938
all_values[4]	auto[0]	auto[0]	1118	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	493	1		T4	1		T21	1		T31	1
all_values[4]	auto[1]	auto[0]	173223	1		T6	1170		T7	1745		T8	4938
all_values[4]	auto[1]	auto[1]	96150	1		T6	547		T7	1745		T8	1646
all_values[5]	auto[0]	auto[0]	1502	1		T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	115	1		T36	1		T37	1		T92	1
all_values[5]	auto[1]	auto[0]	269306	1		T6	1717		T7	3490		T8	6584
all_values[5]	auto[1]	auto[1]	61	1		T257	4		T319	1		T321	3