Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	241466	1		T1	45		T2	37		T3	7
auto[FlashEraseBank]	265581	1		T1	1		T2	15		T3	9

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	252763	1		T2	33		T3	14		T6	547
auto[FlashOpProgram]	234142	1		T1	46		T3	2		T19	1
auto[FlashOpErase]	16142	1		T2	19		T12	1		T4	42
auto[FlashOpInvalid]	4000	1		T135	200		T272	200		T125	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	252763	1		T2	33		T3	14		T6	547
op[FlashOpProgram]	234142	1		T1	46		T3	2		T19	1
op[FlashOpErase]	16142	1		T2	19		T12	1		T4	42
read_erase_read	555	1		T2	17		T4	10		T31	2
read_prog_read	861	1		T3	2		T4	4		T13	3

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	366181	1		T1	44		T2	17		T3	1
auto[FlashPartInfo]	137057	1		T1	1		T2	35		T3	14
auto[FlashPartInfo1]	871	1		T23	1		T75	1		T56	6
auto[FlashPartInfo2]	2938	1		T1	1		T3	1		T23	4

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	181565	1		T2	9		T3	1		T4	40
auto[FlashPartData]	auto[FlashOpProgram]	177159	1		T1	44		T4	30		T5	222
auto[FlashPartData]	auto[FlashOpErase]	3563	1		T2	8		T12	1		T4	25
auto[FlashPartData]	auto[FlashOpInvalid]	3894	1		T135	190		T272	198		T125	196
auto[FlashPartInfo]	auto[FlashOpRead]	68504	1		T2	24		T3	12		T6	547
auto[FlashPartInfo]	auto[FlashOpProgram]	55925	1		T1	1		T3	2		T19	1
auto[FlashPartInfo]	auto[FlashOpErase]	12544	1		T2	11		T4	17		T31	12
auto[FlashPartInfo]	auto[FlashOpInvalid]	84	1		T135	10		T272	2		T125	2
auto[FlashPartInfo1]	auto[FlashOpRead]	690	1		T23	1		T56	6		T130	19
auto[FlashPartInfo1]	auto[FlashOpProgram]	167	1		T75	1		T125	1		T118	1
auto[FlashPartInfo1]	auto[FlashOpErase]	6	1		T125	1		T119	1		T120	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	8	1		T125	2		T120	2		T142	2
auto[FlashPartInfo2]	auto[FlashOpRead]	2004	1		T3	1		T23	4		T26	2
auto[FlashPartInfo2]	auto[FlashOpProgram]	891	1		T1	1		T56	5		T28	3
auto[FlashPartInfo2]	auto[FlashOpErase]	29	1		T131	1		T148	1		T402	2
auto[FlashPartInfo2]	auto[FlashOpInvalid]	14	1		T120	2		T403	2		T142	2