Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31875	1		T3	1		T4	12		T20	2
auto[1]	12	1		T153	5		T404	1		T405	1
auto[2]	78	1		T25	1		T134	2		T154	4
auto[3]	279	1		T2	12		T3	1		T26	23

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8066	1		T2	2		T3	1		T4	3
evic_idx[1]	8070	1		T2	4		T4	3		T13	1
evic_idx[2]	8055	1		T2	3		T4	3		T20	1
evic_idx[3]	8053	1		T2	3		T3	1		T4	3

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31300	1		T2	12		T20	2		T45	480
evic_op[2]	302	1		T3	2		T59	20		T25	2

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7759	1		T45	120		T46	1		T94	66
evic_idx[0]	evic_op[1]	auto[1]	2	1		T153	2		-	-		-	-
evic_idx[0]	evic_op[1]	auto[2]	7	1		T402	1		T406	4		T407	2
evic_idx[0]	evic_op[1]	auto[3]	62	1		T2	2		T26	5		T224	3
evic_idx[0]	evic_op[2]	auto[0]	59	1		T59	5		T221	4		T97	1
evic_idx[0]	evic_op[2]	auto[1]	2	1		T405	1		T408	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	4	1		T134	2		T409	1		T410	1
evic_idx[0]	evic_op[2]	auto[3]	11	1		T3	1		T375	1		T146	1
evic_idx[1]	evic_op[1]	auto[0]	7757	1		T45	120		T46	1		T94	66
evic_idx[1]	evic_op[1]	auto[1]	1	1		T153	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[2]	8	1		T402	2		T406	3		T407	3
evic_idx[1]	evic_op[1]	auto[3]	65	1		T2	4		T26	6		T224	4
evic_idx[1]	evic_op[2]	auto[0]	58	1		T59	5		T221	4		T155	4
evic_idx[1]	evic_op[2]	auto[1]	2	1		T404	1		T408	1		-	-
evic_idx[1]	evic_op[2]	auto[2]	4	1		T25	1		T409	1		T411	1
evic_idx[1]	evic_op[2]	auto[3]	14	1		T25	1		T27	1		T215	1
evic_idx[2]	evic_op[1]	auto[0]	7757	1		T20	1		T45	120		T46	1
evic_idx[2]	evic_op[1]	auto[1]	1	1		T153	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[2]	10	1		T402	1		T406	6		T407	3
evic_idx[2]	evic_op[1]	auto[3]	57	1		T2	3		T26	7		T224	3
evic_idx[2]	evic_op[2]	auto[0]	59	1		T59	5		T221	4		T155	4
evic_idx[2]	evic_op[2]	auto[1]	1	1		T408	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[2]	1	1		T412	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[3]	8	1		T132	1		T413	1		T414	1
evic_idx[3]	evic_op[1]	auto[0]	7758	1		T20	1		T45	120		T46	1
evic_idx[3]	evic_op[1]	auto[1]	1	1		T153	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[2]	7	1		T406	4		T407	3		-	-
evic_idx[3]	evic_op[1]	auto[3]	48	1		T2	3		T26	5		T224	3
evic_idx[3]	evic_op[2]	auto[0]	62	1		T3	1		T59	5		T221	4
evic_idx[3]	evic_op[2]	auto[1]	2	1		T408	1		T415	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	1	1		T416	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[3]	14	1		T134	1		T417	1		T418	1