Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	20314	1		T323	15541		T324	2721		T325	2052
rd_lvl[2]	22475	1		T326	1148		T323	11467		T324	2459
rd_lvl[3]	11912	1		T326	394		T324	1393		T327	1277
rd_lvl[4]	29127	1		T228	1211		T326	45		T328	5637
rd_lvl[5]	12122	1		T6	586		T8	2371		T228	331
rd_lvl[6]	19944	1		T6	229		T8	1186		T48	524
rd_lvl[7]	4584	1		T6	39		T48	146		T228	184
rd_lvl[8]	6208	1		T6	214		T165	115		T326	1
rd_lvl[9]	5750	1		T48	163		T165	11		T329	513
rd_lvl[10]	11342	1		T48	162		T204	1558		T326	3
rd_lvl[11]	5607	1		T6	215		T7	725		T326	2
rd_lvl[12]	5821	1		T7	1020		T228	184		T35	730
rd_lvl[13]	2643	1		T35	124		T326	86		T330	590
rd_lvl[14]	3971	1		T32	244		T330	1106		T86	908
rd_lvl[15]	3360	1		T32	91		T34	407		T35	2