Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	270984	1		T1	1		T2	1		T3	1
all_pins[1]	270984	1		T1	1		T2	1		T3	1
all_pins[2]	270984	1		T1	1		T2	1		T3	1
all_pins[3]	270984	1		T1	1		T2	1		T3	1
all_pins[4]	270984	1		T1	1		T2	1		T3	1
all_pins[5]	270984	1		T1	1		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1349491	1		T1	6		T2	6		T3	6
values[0x1]	276413	1		T6	1849		T7	3490		T8	5277
transitions[0x0=>0x1]	248934	1		T6	1574		T7	3490		T8	5203
transitions[0x1=>0x0]	248918	1		T6	1574		T7	3490		T8	5203

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	270822	1		T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	162	1		T255	4		T256	2		T257	5
all_pins[0]	transitions[0x0=>0x1]	91	1		T255	3		T256	2		T257	2
all_pins[0]	transitions[0x1=>0x0]	74	1		T255	2		T256	3		T257	3
all_pins[1]	values[0x0]	270839	1		T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	145	1		T255	3		T256	3		T257	6
all_pins[1]	transitions[0x0=>0x1]	125	1		T255	1		T256	3		T257	6
all_pins[1]	transitions[0x1=>0x0]	4094	1		T32	22		T34	576		T333	1221
all_pins[2]	values[0x0]	266870	1		T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	4114	1		T32	22		T34	576		T333	1221
all_pins[2]	transitions[0x0=>0x1]	32	1		T255	3		T256	1		T257	1
all_pins[2]	transitions[0x1=>0x0]	165233	1		T6	1283		T7	1745		T8	3557
all_pins[3]	values[0x0]	101669	1		T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	169315	1		T6	1283		T7	1745		T8	3557
all_pins[3]	transitions[0x0=>0x1]	146055	1		T6	1008		T7	1745		T8	3483
all_pins[3]	transitions[0x1=>0x0]	79356	1		T6	291		T7	1745		T8	1646
all_pins[4]	values[0x0]	168368	1		T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	102616	1		T6	566		T7	1745		T8	1720
all_pins[4]	transitions[0x0=>0x1]	102607	1		T6	566		T7	1745		T8	1720
all_pins[4]	transitions[0x1=>0x0]	52	1		T257	2		T319	1		T321	2
all_pins[5]	values[0x0]	270923	1		T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	61	1		T257	4		T319	1		T321	3
all_pins[5]	transitions[0x0=>0x1]	24	1		T257	1		T321	3		T322	1
all_pins[5]	transitions[0x1=>0x0]	109	1		T255	3		T256	2		T257	2