| T1071 |
/workspace/coverage/default/4.flash_ctrl_config_regwen.2446585209 |
|
|
Jul 20 05:31:09 PM PDT 24 |
Jul 20 05:31:24 PM PDT 24 |
26372000 ps |
| T1072 |
/workspace/coverage/default/5.flash_ctrl_disable.3777671341 |
|
|
Jul 20 05:31:35 PM PDT 24 |
Jul 20 05:31:58 PM PDT 24 |
36296800 ps |
| T1073 |
/workspace/coverage/default/0.flash_ctrl_mp_regions.2632750267 |
|
|
Jul 20 05:30:04 PM PDT 24 |
Jul 20 05:34:51 PM PDT 24 |
8483193200 ps |
| T1074 |
/workspace/coverage/default/2.flash_ctrl_ro_serr.3888012449 |
|
|
Jul 20 05:30:29 PM PDT 24 |
Jul 20 05:33:13 PM PDT 24 |
3000358800 ps |
| T183 |
/workspace/coverage/default/1.flash_ctrl_hw_rma_reset.1938612243 |
|
|
Jul 20 05:30:15 PM PDT 24 |
Jul 20 05:43:51 PM PDT 24 |
210191191700 ps |
| T1075 |
/workspace/coverage/default/7.flash_ctrl_intr_wr.2087826257 |
|
|
Jul 20 05:31:41 PM PDT 24 |
Jul 20 05:33:00 PM PDT 24 |
5148034000 ps |
| T1076 |
/workspace/coverage/default/8.flash_ctrl_hw_read_seed_err.2159088048 |
|
|
Jul 20 05:32:14 PM PDT 24 |
Jul 20 05:32:28 PM PDT 24 |
14841900 ps |
| T1077 |
/workspace/coverage/default/33.flash_ctrl_otp_reset.3684988847 |
|
|
Jul 20 05:35:51 PM PDT 24 |
Jul 20 05:37:40 PM PDT 24 |
71530300 ps |
| T1078 |
/workspace/coverage/default/9.flash_ctrl_lcmgr_intg.2498939298 |
|
|
Jul 20 05:32:31 PM PDT 24 |
Jul 20 05:32:45 PM PDT 24 |
26076700 ps |
| T1079 |
/workspace/coverage/default/77.flash_ctrl_otp_reset.219336232 |
|
|
Jul 20 05:37:14 PM PDT 24 |
Jul 20 05:39:03 PM PDT 24 |
41020400 ps |
| T1080 |
/workspace/coverage/default/11.flash_ctrl_hw_read_seed_err.1301555412 |
|
|
Jul 20 05:32:53 PM PDT 24 |
Jul 20 05:33:07 PM PDT 24 |
15393900 ps |
| T1081 |
/workspace/coverage/default/8.flash_ctrl_wo.2130852760 |
|
|
Jul 20 05:31:54 PM PDT 24 |
Jul 20 05:34:37 PM PDT 24 |
7589062600 ps |
| T1082 |
/workspace/coverage/default/8.flash_ctrl_rw_evict.479549860 |
|
|
Jul 20 05:32:07 PM PDT 24 |
Jul 20 05:32:37 PM PDT 24 |
65893000 ps |
| T1083 |
/workspace/coverage/default/24.flash_ctrl_hw_sec_otp.668358278 |
|
|
Jul 20 05:34:49 PM PDT 24 |
Jul 20 05:36:49 PM PDT 24 |
23815321100 ps |
| T1084 |
/workspace/coverage/default/16.flash_ctrl_sec_info_access.2162918065 |
|
|
Jul 20 05:33:53 PM PDT 24 |
Jul 20 05:35:07 PM PDT 24 |
757568300 ps |
| T1085 |
/workspace/coverage/default/4.flash_ctrl_smoke.277518899 |
|
|
Jul 20 05:30:37 PM PDT 24 |
Jul 20 05:33:52 PM PDT 24 |
23233200 ps |
| T1086 |
/workspace/coverage/default/24.flash_ctrl_smoke.3411957395 |
|
|
Jul 20 05:34:46 PM PDT 24 |
Jul 20 05:37:36 PM PDT 24 |
143826700 ps |
| T1087 |
/workspace/coverage/default/35.flash_ctrl_connect.3853548754 |
|
|
Jul 20 05:36:00 PM PDT 24 |
Jul 20 05:36:16 PM PDT 24 |
37111300 ps |
| T1088 |
/workspace/coverage/default/2.flash_ctrl_smoke_hw.769580362 |
|
|
Jul 20 05:30:23 PM PDT 24 |
Jul 20 05:30:47 PM PDT 24 |
40351900 ps |
| T1089 |
/workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.3264410051 |
|
|
Jul 20 05:30:40 PM PDT 24 |
Jul 20 05:31:13 PM PDT 24 |
42447800 ps |
| T1090 |
/workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.2682016916 |
|
|
Jul 20 05:32:07 PM PDT 24 |
Jul 20 05:32:37 PM PDT 24 |
39846800 ps |
| T1091 |
/workspace/coverage/default/7.flash_ctrl_disable.3771280190 |
|
|
Jul 20 05:31:49 PM PDT 24 |
Jul 20 05:32:13 PM PDT 24 |
10975000 ps |
| T1092 |
/workspace/coverage/default/30.flash_ctrl_hw_sec_otp.3340264876 |
|
|
Jul 20 05:35:28 PM PDT 24 |
Jul 20 05:36:26 PM PDT 24 |
8058998200 ps |
| T396 |
/workspace/coverage/default/24.flash_ctrl_sec_info_access.2514769894 |
|
|
Jul 20 05:34:57 PM PDT 24 |
Jul 20 05:35:59 PM PDT 24 |
480410700 ps |
| T1093 |
/workspace/coverage/default/22.flash_ctrl_rw_evict.2665584696 |
|
|
Jul 20 05:34:46 PM PDT 24 |
Jul 20 05:35:16 PM PDT 24 |
36971600 ps |
| T1094 |
/workspace/coverage/default/2.flash_ctrl_alert_test.4116340326 |
|
|
Jul 20 05:30:38 PM PDT 24 |
Jul 20 05:30:54 PM PDT 24 |
68007300 ps |
| T1095 |
/workspace/coverage/default/43.flash_ctrl_sec_info_access.1381282698 |
|
|
Jul 20 05:36:23 PM PDT 24 |
Jul 20 05:37:28 PM PDT 24 |
525243700 ps |
| T1096 |
/workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.2456531409 |
|
|
Jul 20 05:31:06 PM PDT 24 |
Jul 20 05:33:29 PM PDT 24 |
22966240200 ps |
| T1097 |
/workspace/coverage/default/5.flash_ctrl_hw_sec_otp.1738103940 |
|
|
Jul 20 05:31:21 PM PDT 24 |
Jul 20 05:35:30 PM PDT 24 |
6472715200 ps |
| T1098 |
/workspace/coverage/default/11.flash_ctrl_mp_regions.353698108 |
|
|
Jul 20 05:32:46 PM PDT 24 |
Jul 20 05:42:21 PM PDT 24 |
9328329800 ps |
| T1099 |
/workspace/coverage/default/2.flash_ctrl_rw_derr.4184008153 |
|
|
Jul 20 05:30:30 PM PDT 24 |
Jul 20 05:41:04 PM PDT 24 |
16020123700 ps |
| T410 |
/workspace/coverage/default/4.flash_ctrl_rw_evict.505193020 |
|
|
Jul 20 05:31:09 PM PDT 24 |
Jul 20 05:31:41 PM PDT 24 |
31254600 ps |
| T1100 |
/workspace/coverage/default/9.flash_ctrl_phy_arb.107581690 |
|
|
Jul 20 05:32:14 PM PDT 24 |
Jul 20 05:40:12 PM PDT 24 |
1379654300 ps |
| T1101 |
/workspace/coverage/default/16.flash_ctrl_invalid_op.1229267749 |
|
|
Jul 20 05:33:48 PM PDT 24 |
Jul 20 05:35:00 PM PDT 24 |
3831041700 ps |
| T1102 |
/workspace/coverage/default/0.flash_ctrl_hw_rma.2269813480 |
|
|
Jul 20 05:30:04 PM PDT 24 |
Jul 20 06:01:32 PM PDT 24 |
334811525700 ps |
| T1103 |
/workspace/coverage/default/47.flash_ctrl_sec_info_access.1204245803 |
|
|
Jul 20 05:36:41 PM PDT 24 |
Jul 20 05:37:48 PM PDT 24 |
1132054800 ps |
| T1104 |
/workspace/coverage/default/5.flash_ctrl_ro.3242735438 |
|
|
Jul 20 05:31:20 PM PDT 24 |
Jul 20 05:33:17 PM PDT 24 |
789391700 ps |
| T1105 |
/workspace/coverage/default/43.flash_ctrl_alert_test.399916198 |
|
|
Jul 20 05:36:34 PM PDT 24 |
Jul 20 05:36:48 PM PDT 24 |
92273200 ps |
| T1106 |
/workspace/coverage/default/19.flash_ctrl_mp_regions.924284643 |
|
|
Jul 20 05:34:24 PM PDT 24 |
Jul 20 05:41:52 PM PDT 24 |
14154180900 ps |
| T1107 |
/workspace/coverage/default/41.flash_ctrl_hw_sec_otp.4153040367 |
|
|
Jul 20 05:36:12 PM PDT 24 |
Jul 20 05:38:16 PM PDT 24 |
17129488700 ps |
| T255 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.4149990370 |
|
|
Jul 20 04:43:37 PM PDT 24 |
Jul 20 04:43:51 PM PDT 24 |
50161500 ps |
| T67 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.764659678 |
|
|
Jul 20 04:43:16 PM PDT 24 |
Jul 20 04:50:57 PM PDT 24 |
172509200 ps |
| T256 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.727995879 |
|
|
Jul 20 04:43:44 PM PDT 24 |
Jul 20 04:43:58 PM PDT 24 |
16403800 ps |
| T68 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1867165309 |
|
|
Jul 20 04:43:09 PM PDT 24 |
Jul 20 04:43:31 PM PDT 24 |
640545400 ps |
| T69 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.1001387321 |
|
|
Jul 20 04:43:15 PM PDT 24 |
Jul 20 04:44:04 PM PDT 24 |
1615146400 ps |
| T250 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.154851492 |
|
|
Jul 20 04:43:10 PM PDT 24 |
Jul 20 04:44:01 PM PDT 24 |
3471059200 ps |
| T100 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.286286524 |
|
|
Jul 20 04:43:16 PM PDT 24 |
Jul 20 04:49:47 PM PDT 24 |
632357700 ps |
| T101 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.203887531 |
|
|
Jul 20 04:43:54 PM PDT 24 |
Jul 20 04:44:13 PM PDT 24 |
45703400 ps |
| T257 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.3595610636 |
|
|
Jul 20 04:43:14 PM PDT 24 |
Jul 20 04:43:31 PM PDT 24 |
26260500 ps |
| T1108 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1542328342 |
|
|
Jul 20 04:43:45 PM PDT 24 |
Jul 20 04:44:01 PM PDT 24 |
38864900 ps |
| T251 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2779987238 |
|
|
Jul 20 04:43:23 PM PDT 24 |
Jul 20 04:43:41 PM PDT 24 |
40580700 ps |
| T249 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1488305789 |
|
|
Jul 20 04:43:30 PM PDT 24 |
Jul 20 04:43:51 PM PDT 24 |
283516600 ps |
| T252 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1138161655 |
|
|
Jul 20 04:43:33 PM PDT 24 |
Jul 20 04:43:54 PM PDT 24 |
239534900 ps |
| T207 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.343299806 |
|
|
Jul 20 04:43:43 PM PDT 24 |
Jul 20 04:50:09 PM PDT 24 |
182835100 ps |
| T206 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.3099648986 |
|
|
Jul 20 04:43:15 PM PDT 24 |
Jul 20 04:43:34 PM PDT 24 |
121514700 ps |
| T319 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2393946352 |
|
|
Jul 20 04:43:29 PM PDT 24 |
Jul 20 04:43:43 PM PDT 24 |
31597600 ps |
| T208 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1761715168 |
|
|
Jul 20 04:43:37 PM PDT 24 |
Jul 20 04:58:38 PM PDT 24 |
817504400 ps |
| T296 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2894537180 |
|
|
Jul 20 04:43:11 PM PDT 24 |
Jul 20 04:43:30 PM PDT 24 |
77504100 ps |
| T320 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2997715140 |
|
|
Jul 20 04:43:38 PM PDT 24 |
Jul 20 04:43:53 PM PDT 24 |
17818400 ps |
| T321 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.1595716619 |
|
|
Jul 20 04:43:47 PM PDT 24 |
Jul 20 04:44:03 PM PDT 24 |
17468300 ps |
| T322 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3582541416 |
|
|
Jul 20 04:43:47 PM PDT 24 |
Jul 20 04:44:02 PM PDT 24 |
50605800 ps |
| T1109 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.4220286217 |
|
|
Jul 20 04:43:50 PM PDT 24 |
Jul 20 04:44:05 PM PDT 24 |
17554000 ps |
| T1110 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2837544096 |
|
|
Jul 20 04:43:29 PM PDT 24 |
Jul 20 04:43:45 PM PDT 24 |
15555300 ps |
| T1111 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.4148161606 |
|
|
Jul 20 04:43:40 PM PDT 24 |
Jul 20 04:43:56 PM PDT 24 |
12933400 ps |
| T291 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3915899096 |
|
|
Jul 20 04:43:30 PM PDT 24 |
Jul 20 04:43:49 PM PDT 24 |
87985900 ps |
| T1112 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.543895741 |
|
|
Jul 20 04:43:37 PM PDT 24 |
Jul 20 04:43:52 PM PDT 24 |
30069200 ps |
| T235 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.1486575379 |
|
|
Jul 20 04:43:24 PM PDT 24 |
Jul 20 04:51:10 PM PDT 24 |
1644800800 ps |
| T1113 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1307546324 |
|
|
Jul 20 04:43:33 PM PDT 24 |
Jul 20 04:43:50 PM PDT 24 |
41753700 ps |
| T1114 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.3837786382 |
|
|
Jul 20 04:43:52 PM PDT 24 |
Jul 20 04:44:07 PM PDT 24 |
54178800 ps |
| T1115 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3193533166 |
|
|
Jul 20 04:43:35 PM PDT 24 |
Jul 20 04:43:51 PM PDT 24 |
13323400 ps |
| T317 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.134817672 |
|
|
Jul 20 04:43:31 PM PDT 24 |
Jul 20 04:49:56 PM PDT 24 |
183006000 ps |
| T1116 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1639843433 |
|
|
Jul 20 04:43:51 PM PDT 24 |
Jul 20 04:44:06 PM PDT 24 |
17088300 ps |
| T1117 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.3990900503 |
|
|
Jul 20 04:43:16 PM PDT 24 |
Jul 20 04:44:20 PM PDT 24 |
1285775400 ps |
| T229 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2752146319 |
|
|
Jul 20 04:43:08 PM PDT 24 |
Jul 20 04:43:30 PM PDT 24 |
52687400 ps |
| T1118 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.2563464704 |
|
|
Jul 20 04:43:31 PM PDT 24 |
Jul 20 04:43:46 PM PDT 24 |
37694400 ps |
| T239 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2350725365 |
|
|
Jul 20 04:43:30 PM PDT 24 |
Jul 20 04:43:45 PM PDT 24 |
33293800 ps |
| T1119 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.4048534046 |
|
|
Jul 20 04:43:45 PM PDT 24 |
Jul 20 04:44:00 PM PDT 24 |
73918300 ps |
| T234 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1514939284 |
|
|
Jul 20 04:43:37 PM PDT 24 |
Jul 20 04:58:48 PM PDT 24 |
2652753300 ps |
| T292 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2572544610 |
|
|
Jul 20 04:43:20 PM PDT 24 |
Jul 20 04:44:19 PM PDT 24 |
1498032100 ps |
| T1120 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1723885957 |
|
|
Jul 20 04:43:52 PM PDT 24 |
Jul 20 04:44:08 PM PDT 24 |
91472400 ps |
| T1121 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2412731550 |
|
|
Jul 20 04:43:09 PM PDT 24 |
Jul 20 04:43:26 PM PDT 24 |
11366000 ps |
| T1122 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.3265774753 |
|
|
Jul 20 04:43:49 PM PDT 24 |
Jul 20 04:44:08 PM PDT 24 |
363411000 ps |
| T230 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.3055929008 |
|
|
Jul 20 04:43:38 PM PDT 24 |
Jul 20 04:43:56 PM PDT 24 |
39895700 ps |
| T231 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.566617231 |
|
|
Jul 20 04:43:39 PM PDT 24 |
Jul 20 04:43:55 PM PDT 24 |
56393700 ps |
| T1123 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3149279027 |
|
|
Jul 20 04:43:15 PM PDT 24 |
Jul 20 04:44:27 PM PDT 24 |
12610686000 ps |
| T1124 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2411326313 |
|
|
Jul 20 04:43:15 PM PDT 24 |
Jul 20 04:43:31 PM PDT 24 |
35765400 ps |
| T1125 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.4040461704 |
|
|
Jul 20 04:43:43 PM PDT 24 |
Jul 20 04:44:00 PM PDT 24 |
19910200 ps |
| T232 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2550104412 |
|
|
Jul 20 04:43:17 PM PDT 24 |
Jul 20 04:43:37 PM PDT 24 |
91445400 ps |
| T1126 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2991214075 |
|
|
Jul 20 04:43:48 PM PDT 24 |
Jul 20 04:44:09 PM PDT 24 |
58351200 ps |
| T233 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1791021018 |
|
|
Jul 20 04:43:16 PM PDT 24 |
Jul 20 04:43:38 PM PDT 24 |
155001600 ps |
| T248 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3339853731 |
|
|
Jul 20 04:43:34 PM PDT 24 |
Jul 20 04:43:54 PM PDT 24 |
93722900 ps |
| T261 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1098822240 |
|
|
Jul 20 04:43:36 PM PDT 24 |
Jul 20 04:51:19 PM PDT 24 |
731829300 ps |
| T268 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3464122028 |
|
|
Jul 20 04:43:32 PM PDT 24 |
Jul 20 04:51:15 PM PDT 24 |
353688200 ps |
| T1127 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.225204784 |
|
|
Jul 20 04:43:31 PM PDT 24 |
Jul 20 04:43:46 PM PDT 24 |
27443600 ps |
| T293 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2035914834 |
|
|
Jul 20 04:43:41 PM PDT 24 |
Jul 20 04:43:57 PM PDT 24 |
67690800 ps |
| T1128 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.730911248 |
|
|
Jul 20 04:43:20 PM PDT 24 |
Jul 20 04:43:34 PM PDT 24 |
16660300 ps |
| T294 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3219361777 |
|
|
Jul 20 04:43:10 PM PDT 24 |
Jul 20 04:43:39 PM PDT 24 |
75257400 ps |
| T253 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3990986553 |
|
|
Jul 20 04:43:23 PM PDT 24 |
Jul 20 04:43:44 PM PDT 24 |
238973700 ps |
| T1129 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3955886766 |
|
|
Jul 20 04:43:14 PM PDT 24 |
Jul 20 04:43:32 PM PDT 24 |
32708200 ps |
| T240 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.4175418507 |
|
|
Jul 20 04:43:14 PM PDT 24 |
Jul 20 04:43:30 PM PDT 24 |
16200700 ps |
| T1130 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2267004164 |
|
|
Jul 20 04:43:43 PM PDT 24 |
Jul 20 04:44:00 PM PDT 24 |
44609800 ps |
| T1131 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2480450674 |
|
|
Jul 20 04:43:27 PM PDT 24 |
Jul 20 04:44:03 PM PDT 24 |
215119200 ps |
| T1132 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.819758078 |
|
|
Jul 20 04:43:13 PM PDT 24 |
Jul 20 04:43:30 PM PDT 24 |
32911900 ps |
| T1133 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3962558340 |
|
|
Jul 20 04:43:32 PM PDT 24 |
Jul 20 04:43:49 PM PDT 24 |
103526100 ps |
| T295 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.4002489142 |
|
|
Jul 20 04:43:12 PM PDT 24 |
Jul 20 04:44:00 PM PDT 24 |
51509000 ps |
| T1134 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2554481252 |
|
|
Jul 20 04:43:30 PM PDT 24 |
Jul 20 04:43:45 PM PDT 24 |
13466300 ps |
| T1135 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.2433606757 |
|
|
Jul 20 04:43:50 PM PDT 24 |
Jul 20 04:44:05 PM PDT 24 |
49460000 ps |
| T1136 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.327952584 |
|
|
Jul 20 04:43:37 PM PDT 24 |
Jul 20 04:43:55 PM PDT 24 |
175953700 ps |
| T1137 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2369282598 |
|
|
Jul 20 04:43:23 PM PDT 24 |
Jul 20 04:43:37 PM PDT 24 |
47325500 ps |
| T334 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3733745654 |
|
|
Jul 20 04:43:40 PM PDT 24 |
Jul 20 04:51:17 PM PDT 24 |
1944925600 ps |
| T1138 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3692464390 |
|
|
Jul 20 04:43:18 PM PDT 24 |
Jul 20 04:43:33 PM PDT 24 |
33472000 ps |
| T1139 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2215452832 |
|
|
Jul 20 04:43:10 PM PDT 24 |
Jul 20 04:43:30 PM PDT 24 |
62072200 ps |
| T1140 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3654837890 |
|
|
Jul 20 04:43:48 PM PDT 24 |
Jul 20 04:44:03 PM PDT 24 |
28449500 ps |
| T271 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.173803978 |
|
|
Jul 20 04:43:12 PM PDT 24 |
Jul 20 04:55:53 PM PDT 24 |
1350669200 ps |
| T1141 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3903403622 |
|
|
Jul 20 04:43:44 PM PDT 24 |
Jul 20 04:44:00 PM PDT 24 |
88359200 ps |
| T241 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.4029242294 |
|
|
Jul 20 04:43:14 PM PDT 24 |
Jul 20 04:43:30 PM PDT 24 |
14747900 ps |
| T1142 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.368944424 |
|
|
Jul 20 04:43:25 PM PDT 24 |
Jul 20 04:43:41 PM PDT 24 |
117273300 ps |
| T1143 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.4063320484 |
|
|
Jul 20 04:43:38 PM PDT 24 |
Jul 20 04:43:53 PM PDT 24 |
15854400 ps |
| T1144 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1539453542 |
|
|
Jul 20 04:43:22 PM PDT 24 |
Jul 20 04:43:39 PM PDT 24 |
78002800 ps |
| T297 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3883488121 |
|
|
Jul 20 04:43:09 PM PDT 24 |
Jul 20 04:44:04 PM PDT 24 |
1713676600 ps |
| T1145 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1276822629 |
|
|
Jul 20 04:43:14 PM PDT 24 |
Jul 20 04:43:34 PM PDT 24 |
233983400 ps |
| T1146 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1904260363 |
|
|
Jul 20 04:43:22 PM PDT 24 |
Jul 20 04:43:40 PM PDT 24 |
139639100 ps |
| T1147 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.3807936626 |
|
|
Jul 20 04:43:46 PM PDT 24 |
Jul 20 04:44:01 PM PDT 24 |
47574800 ps |
| T1148 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.734443676 |
|
|
Jul 20 04:43:23 PM PDT 24 |
Jul 20 04:43:40 PM PDT 24 |
21352600 ps |
| T1149 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.701326088 |
|
|
Jul 20 04:43:19 PM PDT 24 |
Jul 20 04:43:58 PM PDT 24 |
26906600 ps |
| T1150 |
/workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.445627711 |
|
|
Jul 20 04:43:41 PM PDT 24 |
Jul 20 04:43:55 PM PDT 24 |
17492900 ps |
| T262 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2516524790 |
|
|
Jul 20 04:43:30 PM PDT 24 |
Jul 20 04:51:06 PM PDT 24 |
337645300 ps |
| T1151 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1537545575 |
|
|
Jul 20 04:43:09 PM PDT 24 |
Jul 20 04:43:27 PM PDT 24 |
17422600 ps |
| T267 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.670386924 |
|
|
Jul 20 04:43:29 PM PDT 24 |
Jul 20 04:43:46 PM PDT 24 |
88370900 ps |
| T1152 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2758255505 |
|
|
Jul 20 04:43:34 PM PDT 24 |
Jul 20 04:43:51 PM PDT 24 |
17654500 ps |
| T242 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2774321365 |
|
|
Jul 20 04:43:19 PM PDT 24 |
Jul 20 04:43:33 PM PDT 24 |
29647300 ps |
| T1153 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1775345471 |
|
|
Jul 20 04:43:39 PM PDT 24 |
Jul 20 04:43:53 PM PDT 24 |
52700400 ps |
| T259 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.785628303 |
|
|
Jul 20 04:43:22 PM PDT 24 |
Jul 20 04:43:40 PM PDT 24 |
69247700 ps |
| T260 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3818799839 |
|
|
Jul 20 04:43:45 PM PDT 24 |
Jul 20 04:44:04 PM PDT 24 |
49317200 ps |
| T1154 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2397724746 |
|
|
Jul 20 04:43:13 PM PDT 24 |
Jul 20 04:43:29 PM PDT 24 |
14628400 ps |
| T1155 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.558459606 |
|
|
Jul 20 04:43:34 PM PDT 24 |
Jul 20 04:43:51 PM PDT 24 |
32095600 ps |
| T266 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3849712599 |
|
|
Jul 20 04:43:45 PM PDT 24 |
Jul 20 04:44:04 PM PDT 24 |
134108300 ps |
| T1156 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3779627014 |
|
|
Jul 20 04:43:37 PM PDT 24 |
Jul 20 04:43:58 PM PDT 24 |
128407800 ps |
| T1157 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.2949465778 |
|
|
Jul 20 04:43:47 PM PDT 24 |
Jul 20 04:44:02 PM PDT 24 |
47221600 ps |
| T1158 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.1664602693 |
|
|
Jul 20 04:43:42 PM PDT 24 |
Jul 20 04:43:56 PM PDT 24 |
45347500 ps |
| T1159 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.4285634042 |
|
|
Jul 20 04:43:23 PM PDT 24 |
Jul 20 04:43:37 PM PDT 24 |
238129000 ps |
| T1160 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1590001078 |
|
|
Jul 20 04:43:10 PM PDT 24 |
Jul 20 04:43:27 PM PDT 24 |
68343800 ps |
| T298 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.4193058790 |
|
|
Jul 20 04:43:24 PM PDT 24 |
Jul 20 04:43:40 PM PDT 24 |
106193700 ps |
| T243 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.2026083715 |
|
|
Jul 20 04:43:20 PM PDT 24 |
Jul 20 04:43:34 PM PDT 24 |
27329800 ps |
| T1161 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.2359429609 |
|
|
Jul 20 04:43:47 PM PDT 24 |
Jul 20 04:44:02 PM PDT 24 |
17148700 ps |
| T1162 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1686748539 |
|
|
Jul 20 04:43:44 PM PDT 24 |
Jul 20 04:44:00 PM PDT 24 |
15110600 ps |
| T1163 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.2289025429 |
|
|
Jul 20 04:43:51 PM PDT 24 |
Jul 20 04:44:06 PM PDT 24 |
23553500 ps |
| T254 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1820412952 |
|
|
Jul 20 04:43:16 PM PDT 24 |
Jul 20 04:43:36 PM PDT 24 |
74643700 ps |
| T265 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3287574539 |
|
|
Jul 20 04:43:41 PM PDT 24 |
Jul 20 04:43:59 PM PDT 24 |
53016300 ps |
| T1164 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3009577923 |
|
|
Jul 20 04:43:54 PM PDT 24 |
Jul 20 04:44:09 PM PDT 24 |
52192800 ps |
| T258 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.2922507692 |
|
|
Jul 20 04:43:44 PM PDT 24 |
Jul 20 04:44:04 PM PDT 24 |
239035100 ps |
| T337 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3079943861 |
|
|
Jul 20 04:43:44 PM PDT 24 |
Jul 20 04:56:23 PM PDT 24 |
3865643000 ps |
| T1165 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.4130401162 |
|
|
Jul 20 04:43:38 PM PDT 24 |
Jul 20 04:43:53 PM PDT 24 |
113057000 ps |
| T269 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3252740819 |
|
|
Jul 20 04:43:08 PM PDT 24 |
Jul 20 04:43:28 PM PDT 24 |
484865800 ps |
| T335 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2055945540 |
|
|
Jul 20 04:43:10 PM PDT 24 |
Jul 20 04:58:07 PM PDT 24 |
2639910700 ps |
| T1166 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2317463387 |
|
|
Jul 20 04:43:52 PM PDT 24 |
Jul 20 04:44:07 PM PDT 24 |
17973000 ps |
| T299 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3065235809 |
|
|
Jul 20 04:43:37 PM PDT 24 |
Jul 20 04:43:53 PM PDT 24 |
54809600 ps |
| T264 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2663395130 |
|
|
Jul 20 04:43:46 PM PDT 24 |
Jul 20 04:44:06 PM PDT 24 |
452338000 ps |
| T1167 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.344760114 |
|
|
Jul 20 04:43:46 PM PDT 24 |
Jul 20 04:44:01 PM PDT 24 |
47591300 ps |
| T1168 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.4247383538 |
|
|
Jul 20 04:43:07 PM PDT 24 |
Jul 20 04:43:22 PM PDT 24 |
26278700 ps |
| T300 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.646049600 |
|
|
Jul 20 04:43:22 PM PDT 24 |
Jul 20 04:43:39 PM PDT 24 |
238833000 ps |
| T1169 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1038104488 |
|
|
Jul 20 04:43:21 PM PDT 24 |
Jul 20 04:43:39 PM PDT 24 |
51287500 ps |
| T1170 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2139648634 |
|
|
Jul 20 04:43:35 PM PDT 24 |
Jul 20 04:43:53 PM PDT 24 |
468995500 ps |
| T301 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.78920299 |
|
|
Jul 20 04:43:41 PM PDT 24 |
Jul 20 04:44:00 PM PDT 24 |
60898000 ps |
| T263 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1925128967 |
|
|
Jul 20 04:43:21 PM PDT 24 |
Jul 20 04:43:42 PM PDT 24 |
58658100 ps |
| T1171 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.2855868913 |
|
|
Jul 20 04:43:52 PM PDT 24 |
Jul 20 04:44:07 PM PDT 24 |
22168800 ps |
| T1172 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1990943672 |
|
|
Jul 20 04:43:31 PM PDT 24 |
Jul 20 04:43:47 PM PDT 24 |
24918600 ps |
| T1173 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.916431908 |
|
|
Jul 20 04:43:42 PM PDT 24 |
Jul 20 04:43:58 PM PDT 24 |
39838700 ps |
| T302 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.937023056 |
|
|
Jul 20 04:43:11 PM PDT 24 |
Jul 20 04:43:50 PM PDT 24 |
740560900 ps |
| T1174 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.424345713 |
|
|
Jul 20 04:43:32 PM PDT 24 |
Jul 20 04:43:47 PM PDT 24 |
20855200 ps |
| T1175 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3043046744 |
|
|
Jul 20 04:43:23 PM PDT 24 |
Jul 20 04:43:38 PM PDT 24 |
25865800 ps |
| T1176 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3159410218 |
|
|
Jul 20 04:43:37 PM PDT 24 |
Jul 20 04:43:54 PM PDT 24 |
33508800 ps |
| T1177 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.470037833 |
|
|
Jul 20 04:43:14 PM PDT 24 |
Jul 20 04:43:47 PM PDT 24 |
64889900 ps |
| T1178 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.3965271787 |
|
|
Jul 20 04:43:38 PM PDT 24 |
Jul 20 04:43:56 PM PDT 24 |
35137100 ps |
| T1179 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1674346073 |
|
|
Jul 20 04:43:12 PM PDT 24 |
Jul 20 04:43:30 PM PDT 24 |
11594300 ps |
| T336 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.4065584454 |
|
|
Jul 20 04:43:38 PM PDT 24 |
Jul 20 04:58:45 PM PDT 24 |
2809221800 ps |
| T1180 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.52567018 |
|
|
Jul 20 04:43:12 PM PDT 24 |
Jul 20 04:43:27 PM PDT 24 |
14268400 ps |
| T1181 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.1572158952 |
|
|
Jul 20 04:43:52 PM PDT 24 |
Jul 20 04:44:07 PM PDT 24 |
186489900 ps |
| T1182 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1349202512 |
|
|
Jul 20 04:43:30 PM PDT 24 |
Jul 20 04:43:49 PM PDT 24 |
45937100 ps |
| T1183 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.825855458 |
|
|
Jul 20 04:43:45 PM PDT 24 |
Jul 20 04:44:01 PM PDT 24 |
25523600 ps |
| T1184 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1912995185 |
|
|
Jul 20 04:43:46 PM PDT 24 |
Jul 20 04:44:01 PM PDT 24 |
18657700 ps |
| T1185 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3835047904 |
|
|
Jul 20 04:43:48 PM PDT 24 |
Jul 20 04:44:05 PM PDT 24 |
603197100 ps |
| T1186 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.44625371 |
|
|
Jul 20 04:43:47 PM PDT 24 |
Jul 20 04:44:02 PM PDT 24 |
32527600 ps |
| T1187 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.1282048516 |
|
|
Jul 20 04:43:48 PM PDT 24 |
Jul 20 04:44:03 PM PDT 24 |
52817600 ps |
| T1188 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2951939089 |
|
|
Jul 20 04:43:11 PM PDT 24 |
Jul 20 04:58:15 PM PDT 24 |
2572500400 ps |
| T1189 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1154272525 |
|
|
Jul 20 04:43:16 PM PDT 24 |
Jul 20 04:44:13 PM PDT 24 |
636388900 ps |
| T1190 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2953838454 |
|
|
Jul 20 04:43:42 PM PDT 24 |
Jul 20 04:43:56 PM PDT 24 |
38018400 ps |
| T1191 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2992953646 |
|
|
Jul 20 04:43:43 PM PDT 24 |
Jul 20 04:43:59 PM PDT 24 |
35530700 ps |
| T1192 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.105046672 |
|
|
Jul 20 04:43:07 PM PDT 24 |
Jul 20 04:43:21 PM PDT 24 |
30165700 ps |
| T270 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2039978326 |
|
|
Jul 20 04:43:40 PM PDT 24 |
Jul 20 04:44:00 PM PDT 24 |
516737200 ps |
| T1193 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2846202427 |
|
|
Jul 20 04:43:39 PM PDT 24 |
Jul 20 04:43:59 PM PDT 24 |
107758600 ps |
| T1194 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1663792976 |
|
|
Jul 20 04:43:43 PM PDT 24 |
Jul 20 04:44:04 PM PDT 24 |
514309400 ps |
| T1195 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.26460492 |
|
|
Jul 20 04:43:11 PM PDT 24 |
Jul 20 04:43:30 PM PDT 24 |
34199900 ps |
| T1196 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2341917820 |
|
|
Jul 20 04:43:48 PM PDT 24 |
Jul 20 04:44:07 PM PDT 24 |
150936400 ps |
| T1197 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3714984234 |
|
|
Jul 20 04:43:12 PM PDT 24 |
Jul 20 04:43:34 PM PDT 24 |
57360000 ps |
| T1198 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1383220000 |
|
|
Jul 20 04:43:38 PM PDT 24 |
Jul 20 04:43:55 PM PDT 24 |
16978000 ps |
| T1199 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.966411985 |
|
|
Jul 20 04:43:31 PM PDT 24 |
Jul 20 04:44:07 PM PDT 24 |
2210819900 ps |
| T1200 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1187113674 |
|
|
Jul 20 04:43:47 PM PDT 24 |
Jul 20 04:44:05 PM PDT 24 |
91931000 ps |
| T1201 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1357588266 |
|
|
Jul 20 04:43:46 PM PDT 24 |
Jul 20 04:44:04 PM PDT 24 |
122204800 ps |
| T1202 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.622269811 |
|
|
Jul 20 04:43:46 PM PDT 24 |
Jul 20 04:44:03 PM PDT 24 |
192425800 ps |
| T1203 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.2168536011 |
|
|
Jul 20 04:43:39 PM PDT 24 |
Jul 20 04:43:54 PM PDT 24 |
51573500 ps |
| T339 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.23429656 |
|
|
Jul 20 04:43:29 PM PDT 24 |
Jul 20 04:56:20 PM PDT 24 |
1617119300 ps |
| T1204 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.933617240 |
|
|
Jul 20 04:43:48 PM PDT 24 |
Jul 20 04:44:04 PM PDT 24 |
28775000 ps |
| T1205 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1421802377 |
|
|
Jul 20 04:43:50 PM PDT 24 |
Jul 20 04:44:05 PM PDT 24 |
11663100 ps |
| T1206 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.638001795 |
|
|
Jul 20 04:43:12 PM PDT 24 |
Jul 20 04:44:14 PM PDT 24 |
1320657800 ps |
| T1207 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1079703990 |
|
|
Jul 20 04:43:40 PM PDT 24 |
Jul 20 04:43:56 PM PDT 24 |
167826100 ps |
| T1208 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.418710436 |
|
|
Jul 20 04:43:40 PM PDT 24 |
Jul 20 04:43:54 PM PDT 24 |
24416600 ps |
| T1209 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2071378225 |
|
|
Jul 20 04:43:40 PM PDT 24 |
Jul 20 04:44:01 PM PDT 24 |
1558761500 ps |
| T1210 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2242749237 |
|
|
Jul 20 04:43:32 PM PDT 24 |
Jul 20 04:43:51 PM PDT 24 |
296469000 ps |
| T1211 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.790010996 |
|
|
Jul 20 04:43:31 PM PDT 24 |
Jul 20 04:43:51 PM PDT 24 |
124581200 ps |
| T1212 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3756503116 |
|
|
Jul 20 04:43:17 PM PDT 24 |
Jul 20 04:44:24 PM PDT 24 |
1593819800 ps |
| T1213 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1107434664 |
|
|
Jul 20 04:43:16 PM PDT 24 |
Jul 20 04:43:33 PM PDT 24 |
22772000 ps |
| T1214 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.3787779624 |
|
|
Jul 20 04:43:49 PM PDT 24 |
Jul 20 04:44:04 PM PDT 24 |
27651500 ps |
| T1215 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3422531955 |
|
|
Jul 20 04:43:11 PM PDT 24 |
Jul 20 04:43:47 PM PDT 24 |
58486300 ps |
| T1216 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.4050576729 |
|
|
Jul 20 04:43:13 PM PDT 24 |
Jul 20 04:43:34 PM PDT 24 |
75472200 ps |
| T1217 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.428523640 |
|
|
Jul 20 04:43:14 PM PDT 24 |
Jul 20 04:43:30 PM PDT 24 |
120018700 ps |
| T1218 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3698871821 |
|
|
Jul 20 04:43:10 PM PDT 24 |
Jul 20 04:43:30 PM PDT 24 |
73689200 ps |
| T1219 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3800421641 |
|
|
Jul 20 04:43:45 PM PDT 24 |
Jul 20 04:44:00 PM PDT 24 |
16045900 ps |
| T1220 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1168573145 |
|
|
Jul 20 04:43:45 PM PDT 24 |
Jul 20 04:44:02 PM PDT 24 |
14788300 ps |
| T1221 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2325966 |
|
|
Jul 20 04:43:14 PM PDT 24 |
Jul 20 04:43:44 PM PDT 24 |
31246100 ps |
| T1222 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.1792422763 |
|
|
Jul 20 04:43:47 PM PDT 24 |
Jul 20 04:44:03 PM PDT 24 |
18433300 ps |
| T1223 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2043506559 |
|
|
Jul 20 04:43:12 PM PDT 24 |
Jul 20 04:43:32 PM PDT 24 |
37587800 ps |
| T1224 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.900216437 |
|
|
Jul 20 04:43:45 PM PDT 24 |
Jul 20 04:44:06 PM PDT 24 |
1004946500 ps |
| T1225 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2159979195 |
|
|
Jul 20 04:43:33 PM PDT 24 |
Jul 20 04:43:51 PM PDT 24 |
58136200 ps |
| T1226 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.2908778655 |
|
|
Jul 20 04:43:41 PM PDT 24 |
Jul 20 04:43:57 PM PDT 24 |
13536700 ps |
| T1227 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3104104474 |
|
|
Jul 20 04:43:16 PM PDT 24 |
Jul 20 04:43:33 PM PDT 24 |
87209200 ps |
| T1228 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3895535804 |
|
|
Jul 20 04:43:12 PM PDT 24 |
Jul 20 04:43:28 PM PDT 24 |
16938000 ps |
| T1229 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.629673338 |
|
|
Jul 20 04:43:26 PM PDT 24 |
Jul 20 04:43:44 PM PDT 24 |
211174300 ps |
| T1230 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1853442623 |
|
|
Jul 20 04:43:40 PM PDT 24 |
Jul 20 04:43:59 PM PDT 24 |
47355000 ps |
| T1231 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.25710614 |
|
|
Jul 20 04:43:52 PM PDT 24 |
Jul 20 04:44:11 PM PDT 24 |
124139800 ps |
| T1232 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.3227433380 |
|
|
Jul 20 04:43:46 PM PDT 24 |
Jul 20 04:44:00 PM PDT 24 |
16976000 ps |
| T1233 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.4084298468 |
|
|
Jul 20 04:43:41 PM PDT 24 |
Jul 20 04:44:00 PM PDT 24 |
294638800 ps |
| T1234 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3193977381 |
|
|
Jul 20 04:43:21 PM PDT 24 |
Jul 20 04:43:38 PM PDT 24 |
38744600 ps |
| T1235 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1333700679 |
|
|
Jul 20 04:43:15 PM PDT 24 |
Jul 20 04:43:30 PM PDT 24 |
42926200 ps |
| T338 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2196539665 |
|
|
Jul 20 04:43:39 PM PDT 24 |
Jul 20 04:58:34 PM PDT 24 |
1454346700 ps |
| T1236 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2316407374 |
|
|
Jul 20 04:43:33 PM PDT 24 |
Jul 20 04:43:48 PM PDT 24 |
25367600 ps |
| T1237 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3155651457 |
|
|
Jul 20 04:43:40 PM PDT 24 |
Jul 20 04:43:58 PM PDT 24 |
142988000 ps |
| T1238 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3122483550 |
|
|
Jul 20 04:43:37 PM PDT 24 |
Jul 20 04:43:53 PM PDT 24 |
12906300 ps |
| T1239 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.3135751772 |
|
|
Jul 20 04:43:31 PM PDT 24 |
Jul 20 04:44:08 PM PDT 24 |
301316200 ps |
| T1240 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3649430015 |
|
|
Jul 20 04:43:41 PM PDT 24 |
Jul 20 04:43:58 PM PDT 24 |
38110500 ps |
| T1241 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.731288953 |
|
|
Jul 20 04:43:18 PM PDT 24 |
Jul 20 04:43:33 PM PDT 24 |
30099300 ps |
| T1242 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1152321252 |
|
|
Jul 20 04:43:22 PM PDT 24 |
Jul 20 04:43:39 PM PDT 24 |
12014900 ps |
| T1243 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2744456821 |
|
|
Jul 20 04:43:34 PM PDT 24 |
Jul 20 04:43:51 PM PDT 24 |
36842900 ps |
| T1244 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.486122211 |
|
|
Jul 20 04:43:38 PM PDT 24 |
Jul 20 04:43:53 PM PDT 24 |
21413200 ps |
| T1245 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.3920648098 |
|
|
Jul 20 04:43:43 PM PDT 24 |
Jul 20 04:44:02 PM PDT 24 |
158139400 ps |
| T1246 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.258055647 |
|
|
Jul 20 04:43:16 PM PDT 24 |
Jul 20 04:49:43 PM PDT 24 |
1495209600 ps |
| T1247 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.3478953965 |
|
|
Jul 20 04:43:54 PM PDT 24 |
Jul 20 04:44:09 PM PDT 24 |
62595300 ps |
| T1248 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.1761415698 |
|
|
Jul 20 04:43:33 PM PDT 24 |
Jul 20 04:43:50 PM PDT 24 |
65011700 ps |
| T1249 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2973740094 |
|
|
Jul 20 04:43:39 PM PDT 24 |
Jul 20 04:43:57 PM PDT 24 |
61424800 ps |
| T1250 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3997291180 |
|
|
Jul 20 04:43:44 PM PDT 24 |
Jul 20 04:43:58 PM PDT 24 |
46430500 ps |