Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	322762	1		T1	2		T2	1		T3	1
all_values[1]	322762	1		T1	2		T2	1		T3	1
all_values[2]	322762	1		T1	2		T2	1		T3	1
all_values[3]	322762	1		T1	2		T2	1		T3	1
all_values[4]	322762	1		T1	2		T2	1		T3	1
all_values[5]	322762	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	651879	1		T1	12		T2	6		T3	6
auto[1]	1284693	1		T26	13432		T36	11264		T37	19896

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	948553	1		T1	7		T2	4		T3	4
auto[1]	988019	1		T1	5		T2	2		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	322608	1		T1	2		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	154	1		T261	2		T262	6		T263	2
all_values[1]	auto[0]	auto[1]	322616	1		T1	2		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	146	1		T261	5		T262	3		T263	2
all_values[2]	auto[0]	auto[0]	1617	1		T1	2		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	56	1		T261	1		T262	1		T263	1
all_values[2]	auto[1]	auto[0]	321037	1		T26	3358		T36	2816		T37	4974
all_values[2]	auto[1]	auto[1]	52	1		T261	2		T262	1		T263	1
all_values[3]	auto[0]	auto[0]	1614	1		T1	2		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	47	1		T262	2		T332	1		T330	1
all_values[3]	auto[1]	auto[0]	89838	1		T26	1679		T36	1408		T37	1658
all_values[3]	auto[1]	auto[1]	231263	1		T26	1679		T36	1408		T37	3316
all_values[4]	auto[0]	auto[0]	1147	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	519	1		T1	1		T18	1		T4	1
all_values[4]	auto[1]	auto[0]	210703	1		T26	1679		T36	1408		T37	3316
all_values[4]	auto[1]	auto[1]	110393	1		T26	1679		T36	1408		T37	1658
all_values[5]	auto[0]	auto[0]	1549	1		T1	2		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	106	1		T38	1		T6	1		T39	1
all_values[5]	auto[1]	auto[0]	321048	1		T26	3358		T36	2816		T37	4974
all_values[5]	auto[1]	auto[1]	59	1		T261	5		T262	1		T263	1