Summary for Variable erase_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for erase_cp
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[FlashErasePage] |
249175 |
1 |
|
T1 |
898 |
|
T2 |
24 |
|
T18 |
783 |
auto[FlashEraseBank] |
274912 |
1 |
|
T1 |
680 |
|
T2 |
19 |
|
T18 |
672 |
Summary for Variable op_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for op_cp
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[FlashOpRead] |
263080 |
1 |
|
T2 |
27 |
|
T4 |
11 |
|
T11 |
1 |
auto[FlashOpProgram] |
240879 |
1 |
|
T1 |
1578 |
|
T18 |
1455 |
|
T4 |
8 |
auto[FlashOpErase] |
16128 |
1 |
|
T2 |
16 |
|
T4 |
2 |
|
T5 |
4 |
auto[FlashOpInvalid] |
4000 |
1 |
|
T77 |
200 |
|
T298 |
200 |
|
T299 |
200 |
Summary for Variable op_evict_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
5 |
0 |
5 |
100.00 |
User Defined Bins for op_evict_cp
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
op[FlashOpRead] |
263080 |
1 |
|
T2 |
27 |
|
T4 |
11 |
|
T11 |
1 |
op[FlashOpProgram] |
240879 |
1 |
|
T1 |
1578 |
|
T18 |
1455 |
|
T4 |
8 |
op[FlashOpErase] |
16128 |
1 |
|
T2 |
16 |
|
T4 |
2 |
|
T5 |
4 |
read_erase_read |
505 |
1 |
|
T2 |
7 |
|
T5 |
1 |
|
T31 |
2 |
read_prog_read |
829 |
1 |
|
T4 |
3 |
|
T20 |
6 |
|
T42 |
1 |
Summary for Variable part_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for part_cp
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[FlashPartData] |
383274 |
1 |
|
T1 |
1393 |
|
T2 |
20 |
|
T18 |
1258 |
auto[FlashPartInfo] |
137647 |
1 |
|
T1 |
176 |
|
T2 |
20 |
|
T18 |
193 |
auto[FlashPartInfo1] |
789 |
1 |
|
T4 |
4 |
|
T6 |
2 |
|
T44 |
1 |
auto[FlashPartInfo2] |
2377 |
1 |
|
T1 |
9 |
|
T2 |
3 |
|
T18 |
4 |
Summary for Cross op_part_cross
Samples crossed: part_cp op_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
1 |
15 |
93.75 |
1 |
Automatically Generated Cross Bins for op_part_cross
Uncovered bins
part_cp | op_cp | COUNT | AT LEAST | NUMBER |
[auto[FlashPartInfo1]] |
[auto[FlashOpInvalid]] |
0 |
1 |
1 |
Covered bins
part_cp | op_cp | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[FlashPartData] |
auto[FlashOpRead] |
192987 |
1 |
|
T2 |
9 |
|
T4 |
5 |
|
T13 |
1 |
auto[FlashPartData] |
auto[FlashOpProgram] |
182712 |
1 |
|
T1 |
1393 |
|
T18 |
1258 |
|
T4 |
4 |
auto[FlashPartData] |
auto[FlashOpErase] |
3641 |
1 |
|
T2 |
11 |
|
T4 |
1 |
|
T24 |
2 |
auto[FlashPartData] |
auto[FlashOpInvalid] |
3934 |
1 |
|
T77 |
196 |
|
T298 |
192 |
|
T299 |
198 |
auto[FlashPartInfo] |
auto[FlashOpRead] |
68003 |
1 |
|
T2 |
16 |
|
T4 |
1 |
|
T11 |
1 |
auto[FlashPartInfo] |
auto[FlashOpProgram] |
57134 |
1 |
|
T1 |
176 |
|
T18 |
193 |
|
T4 |
2 |
auto[FlashPartInfo] |
auto[FlashOpErase] |
12454 |
1 |
|
T2 |
4 |
|
T4 |
1 |
|
T5 |
4 |
auto[FlashPartInfo] |
auto[FlashOpInvalid] |
56 |
1 |
|
T77 |
4 |
|
T298 |
8 |
|
T342 |
2 |
auto[FlashPartInfo1] |
auto[FlashOpRead] |
627 |
1 |
|
T4 |
4 |
|
T6 |
2 |
|
T44 |
1 |
auto[FlashPartInfo1] |
auto[FlashOpProgram] |
160 |
1 |
|
T128 |
32 |
|
T151 |
32 |
|
T152 |
32 |
auto[FlashPartInfo1] |
auto[FlashOpErase] |
2 |
1 |
|
T343 |
1 |
|
T344 |
1 |
|
- |
- |
auto[FlashPartInfo2] |
auto[FlashOpRead] |
1463 |
1 |
|
T2 |
2 |
|
T4 |
1 |
|
T20 |
1 |
auto[FlashPartInfo2] |
auto[FlashOpProgram] |
873 |
1 |
|
T1 |
9 |
|
T18 |
4 |
|
T4 |
2 |
auto[FlashPartInfo2] |
auto[FlashOpErase] |
31 |
1 |
|
T2 |
1 |
|
T144 |
1 |
|
T345 |
4 |
auto[FlashPartInfo2] |
auto[FlashOpInvalid] |
10 |
1 |
|
T299 |
2 |
|
T346 |
2 |
|
T347 |
2 |