Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31799	1		T4	4		T24	5		T25	2
auto[1]	60	1		T2	1		T80	2		T345	1
auto[2]	39	1		T2	6		T221	5		T345	8
auto[3]	200	1		T2	4		T27	1		T218	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8020	1		T2	2		T4	1		T24	1
evic_idx[1]	8023	1		T2	2		T4	1		T24	1
evic_idx[2]	8031	1		T2	3		T4	1		T24	2
evic_idx[3]	8024	1		T2	4		T4	1		T24	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	31262	1		T2	11		T77	400		T96	208
evic_op[2]	337	1		T24	1		T25	2		T27	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[1]]	[evic_op[2]]	[auto[2]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7756	1		T77	100		T96	52		T99	63
evic_idx[0]	evic_op[1]	auto[1]	12	1		T2	1		T348	2		T349	1
evic_idx[0]	evic_op[1]	auto[2]	6	1		T221	2		T345	1		T348	1
evic_idx[0]	evic_op[1]	auto[3]	37	1		T2	1		T221	3		T345	1
evic_idx[0]	evic_op[2]	auto[0]	71	1		T25	2		T62	4		T212	9
evic_idx[0]	evic_op[2]	auto[1]	2	1		T350	1		T351	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	2	1		T220	1		T352	1		-	-
evic_idx[0]	evic_op[2]	auto[3]	9	1		T209	1		T210	1		T353	1
evic_idx[1]	evic_op[1]	auto[0]	7758	1		T77	100		T96	52		T99	63
evic_idx[1]	evic_op[1]	auto[1]	13	1		T348	2		T354	1		T349	1
evic_idx[1]	evic_op[1]	auto[2]	7	1		T2	1		T221	2		T345	1
evic_idx[1]	evic_op[1]	auto[3]	35	1		T2	1		T221	3		T345	1
evic_idx[1]	evic_op[2]	auto[0]	69	1		T62	4		T212	9		T236	1
evic_idx[1]	evic_op[2]	auto[1]	3	1		T80	1		T350	1		T355	1
evic_idx[1]	evic_op[2]	auto[3]	13	1		T27	1		T218	1		T209	1
evic_idx[2]	evic_op[1]	auto[0]	7760	1		T77	100		T96	52		T99	63
evic_idx[2]	evic_op[1]	auto[1]	12	1		T345	1		T348	1		T286	1
evic_idx[2]	evic_op[1]	auto[2]	8	1		T2	2		T345	4		T348	1
evic_idx[2]	evic_op[1]	auto[3]	43	1		T2	1		T221	1		T345	1
evic_idx[2]	evic_op[2]	auto[0]	67	1		T24	1		T62	4		T212	9
evic_idx[2]	evic_op[2]	auto[1]	3	1		T80	1		T350	1		T356	1
evic_idx[2]	evic_op[2]	auto[2]	1	1		T357	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[3]	12	1		T209	1		T318	1		T358	1
evic_idx[3]	evic_op[1]	auto[0]	7756	1		T77	100		T96	52		T99	63
evic_idx[3]	evic_op[1]	auto[1]	13	1		T348	1		T286	1		T354	1
evic_idx[3]	evic_op[1]	auto[2]	8	1		T2	3		T221	1		T345	2
evic_idx[3]	evic_op[1]	auto[3]	38	1		T2	1		T221	3		T345	2
evic_idx[3]	evic_op[2]	auto[0]	67	1		T62	4		T212	9		T230	1
evic_idx[3]	evic_op[2]	auto[1]	2	1		T350	1		T352	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	3	1		T359	1		T360	2		-	-
evic_idx[3]	evic_op[2]	auto[3]	13	1		T209	2		T361	1		T362	1