Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	19371	1		T334	1229		T335	2689		T336	755
rd_lvl[2]	36677	1		T116	1358		T334	2202		T335	2723
rd_lvl[3]	13256	1		T116	717		T334	575		T335	1569
rd_lvl[4]	30025	1		T116	142		T334	1664		T337	5517
rd_lvl[5]	15752	1		T116	467		T334	245		T338	1004
rd_lvl[6]	12123	1		T116	518		T334	1393		T339	477
rd_lvl[7]	17140	1		T37	1872		T116	74		T334	121
rd_lvl[8]	21500	1		T37	1444		T116	74		T334	313
rd_lvl[9]	9503	1		T36	241		T116	73		T334	1111
rd_lvl[10]	10315	1		T36	1167		T334	49		T280	1078
rd_lvl[11]	6021	1		T334	2548		T338	7		T35	76
rd_lvl[12]	9432	1		T116	3		T33	313		T34	38
rd_lvl[13]	3116	1		T116	3		T277	622		T33	161
rd_lvl[14]	7090	1		T26	1312		T277	1015		T276	1307
rd_lvl[15]	1681	1		T26	367		T33	39		T276	249