Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	322762	1		T1	2		T2	1		T3	1
all_pins[1]	322762	1		T1	2		T2	1		T3	1
all_pins[2]	322762	1		T1	2		T2	1		T3	1
all_pins[3]	322762	1		T1	2		T2	1		T3	1
all_pins[4]	322762	1		T1	2		T2	1		T3	1
all_pins[5]	322762	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1606062	1		T1	12		T2	6		T3	6
values[0x1]	330510	1		T26	3358		T36	2816		T37	4974
transitions[0x0=>0x1]	304252	1		T26	3358		T36	2816		T37	4974
transitions[0x1=>0x0]	304238	1		T26	3358		T36	2816		T37	4974

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	322608	1		T1	2		T2	1		T3	1
all_pins[0]	values[0x1]	154	1		T261	2		T262	6		T263	2
all_pins[0]	transitions[0x0=>0x1]	81	1		T261	1		T262	5		T263	1
all_pins[0]	transitions[0x1=>0x0]	73	1		T261	4		T262	2		T263	1
all_pins[1]	values[0x0]	322616	1		T1	2		T2	1		T3	1
all_pins[1]	values[0x1]	146	1		T261	5		T262	3		T263	2
all_pins[1]	transitions[0x0=>0x1]	122	1		T261	4		T262	3		T263	2
all_pins[1]	transitions[0x1=>0x0]	974	1		T363	946		T261	1		T262	1
all_pins[2]	values[0x0]	321764	1		T1	2		T2	1		T3	1
all_pins[2]	values[0x1]	998	1		T363	946		T261	2		T262	1
all_pins[2]	transitions[0x0=>0x1]	39	1		T261	1		T262	1		T263	1
all_pins[2]	transitions[0x1=>0x0]	213069	1		T26	1679		T36	1408		T37	3316
all_pins[3]	values[0x0]	108734	1		T1	2		T2	1		T3	1
all_pins[3]	values[0x1]	214028	1		T26	1679		T36	1408		T37	3316
all_pins[3]	transitions[0x0=>0x1]	188883	1		T26	1679		T36	1408		T37	3316
all_pins[3]	transitions[0x1=>0x0]	89980	1		T26	1679		T36	1408		T37	1658
all_pins[4]	values[0x0]	207637	1		T1	2		T2	1		T3	1
all_pins[4]	values[0x1]	115125	1		T26	1679		T36	1408		T37	1658
all_pins[4]	transitions[0x0=>0x1]	115104	1		T26	1679		T36	1408		T37	1658
all_pins[4]	transitions[0x1=>0x0]	38	1		T261	4		T263	1		T332	4
all_pins[5]	values[0x0]	322703	1		T1	2		T2	1		T3	1
all_pins[5]	values[0x1]	59	1		T261	5		T262	1		T263	1
all_pins[5]	transitions[0x0=>0x1]	23	1		T261	2		T263	1		T332	3
all_pins[5]	transitions[0x1=>0x0]	104	1		T262	4		T263	2		T332	2