Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	435245	1		T1	2		T2	2		T3	1
all_values[1]	435245	1		T1	2		T2	2		T3	1
all_values[2]	435245	1		T1	2		T2	2		T3	1
all_values[3]	435245	1		T1	2		T2	2		T3	1
all_values[4]	435245	1		T1	2		T2	2		T3	1
all_values[5]	435245	1		T1	2		T2	2		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	876610	1		T1	12		T2	12		T3	6
auto[1]	1734860	1		T20	24736		T33	13312		T34	12368

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1279224	1		T1	7		T2	7		T3	4
auto[1]	1332246	1		T1	5		T2	5		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	435087	1		T1	2		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	158	1		T281	4		T282	3		T283	3
all_values[1]	auto[0]	auto[1]	435083	1		T1	2		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	162	1		T281	2		T282	1		T283	5
all_values[2]	auto[0]	auto[0]	1555	1		T1	2		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	57	1		T281	4		T282	3		T350	1
all_values[2]	auto[1]	auto[0]	433581	1		T20	6184		T33	3328		T34	3092
all_values[2]	auto[1]	auto[1]	52	1		T282	1		T283	2		T352	1
all_values[3]	auto[0]	auto[0]	1538	1		T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	58	1		T281	1		T282	2		T352	1
all_values[3]	auto[1]	auto[0]	90230	1		T20	1546		T33	1664		T34	1546
all_values[3]	auto[1]	auto[1]	343419	1		T20	4638		T33	1664		T34	1546
all_values[4]	auto[0]	auto[0]	1121	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	489	1		T1	1		T2	1		T15	1
all_values[4]	auto[1]	auto[0]	316125	1		T20	4638		T33	1664		T34	1546
all_values[4]	auto[1]	auto[1]	117510	1		T20	1546		T33	1664		T34	1546
all_values[5]	auto[0]	auto[0]	1512	1		T1	2		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	110	1		T17	1		T4	1		T19	1
all_values[5]	auto[1]	auto[0]	433562	1		T20	6184		T33	3328		T34	3092
all_values[5]	auto[1]	auto[1]	61	1		T282	2		T283	3		T351	2