Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T17 |
1 |
|
T239 |
1 |
|
T64 |
14 |
| others[1] |
212 |
1 |
|
T392 |
1 |
|
T120 |
1 |
|
T118 |
1 |
| others[2] |
213 |
1 |
|
T59 |
1 |
|
T64 |
13 |
|
T69 |
6 |
| others[3] |
376 |
1 |
|
T393 |
1 |
|
T139 |
2 |
|
T248 |
1 |
| false |
132 |
1 |
|
T248 |
1 |
|
T64 |
3 |
|
T69 |
7 |
| true |
13629 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9075 |
1 |
|
T3 |
1 |
|
T16 |
67 |
|
T18 |
12 |
| others[1] |
1265 |
1 |
|
T18 |
12 |
|
T58 |
19 |
|
T59 |
1 |
| others[2] |
1295 |
1 |
|
T18 |
15 |
|
T58 |
15 |
|
T34 |
1 |
| others[3] |
2042 |
1 |
|
T18 |
20 |
|
T19 |
1 |
|
T33 |
1 |
| false |
635 |
1 |
|
T18 |
3 |
|
T58 |
6 |
|
T59 |
1 |
| true |
467 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9104 |
1 |
|
T16 |
67 |
|
T18 |
16 |
|
T58 |
16 |
| others[1] |
1252 |
1 |
|
T18 |
9 |
|
T58 |
13 |
|
T34 |
1 |
| others[2] |
1256 |
1 |
|
T18 |
12 |
|
T58 |
20 |
|
T59 |
1 |
| others[3] |
2102 |
1 |
|
T18 |
18 |
|
T33 |
1 |
|
T58 |
25 |
| false |
627 |
1 |
|
T18 |
7 |
|
T58 |
13 |
|
T59 |
1 |
| true |
438 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
115 |
1 |
|
T248 |
1 |
|
T64 |
3 |
|
T395 |
1 |
| others[1] |
102 |
1 |
|
T51 |
1 |
|
T139 |
1 |
|
T143 |
1 |
| others[2] |
95 |
1 |
|
T238 |
1 |
|
T64 |
3 |
|
T395 |
1 |
| others[3] |
164 |
1 |
|
T4 |
1 |
|
T59 |
1 |
|
T139 |
1 |
| false |
44 |
1 |
|
T59 |
1 |
|
T143 |
1 |
|
T64 |
2 |
| true |
14259 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
1 |
| others[1] |
215 |
1 |
|
T20 |
1 |
|
T120 |
1 |
|
T165 |
1 |
| others[2] |
254 |
1 |
|
T52 |
1 |
|
T59 |
1 |
|
T299 |
1 |
| others[3] |
391 |
1 |
|
T4 |
1 |
|
T24 |
1 |
|
T59 |
1 |
| false |
118 |
1 |
|
T2 |
1 |
|
T301 |
1 |
|
T64 |
3 |
| true |
13576 |
1 |
|
T16 |
67 |
|
T17 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8885 |
1 |
|
T16 |
67 |
|
T18 |
8 |
|
T4 |
1 |
| others[1] |
1044 |
1 |
|
T18 |
7 |
|
T58 |
18 |
|
T82 |
2 |
| others[2] |
1073 |
1 |
|
T18 |
9 |
|
T58 |
9 |
|
T52 |
1 |
| others[3] |
1779 |
1 |
|
T18 |
8 |
|
T20 |
1 |
|
T33 |
1 |
| false |
568 |
1 |
|
T18 |
3 |
|
T24 |
1 |
|
T58 |
9 |
| true |
1430 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
249 |
1 |
|
T19 |
1 |
|
T20 |
1 |
|
T139 |
1 |
| others[1] |
231 |
1 |
|
T2 |
1 |
|
T24 |
1 |
|
T120 |
1 |
| others[2] |
248 |
1 |
|
T392 |
1 |
|
T118 |
1 |
|
T23 |
1 |
| others[3] |
406 |
1 |
|
T4 |
1 |
|
T51 |
1 |
|
T52 |
1 |
| false |
115 |
1 |
|
T93 |
1 |
|
T64 |
7 |
|
T202 |
1 |
| true |
13530 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T16 |
67 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T137 |
1 |
|
T64 |
9 |
|
T69 |
4 |
| others[1] |
261 |
1 |
|
T59 |
1 |
|
T239 |
1 |
|
T64 |
10 |
| others[2] |
226 |
1 |
|
T143 |
1 |
|
T64 |
10 |
|
T69 |
12 |
| others[3] |
372 |
1 |
|
T17 |
1 |
|
T46 |
1 |
|
T94 |
1 |
| false |
112 |
1 |
|
T64 |
2 |
|
T65 |
1 |
|
T395 |
1 |
| true |
13602 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9123 |
1 |
|
T16 |
67 |
|
T18 |
17 |
|
T58 |
21 |
| others[1] |
1224 |
1 |
|
T17 |
1 |
|
T18 |
12 |
|
T58 |
16 |
| others[2] |
1230 |
1 |
|
T18 |
14 |
|
T33 |
1 |
|
T58 |
13 |
| others[3] |
2100 |
1 |
|
T18 |
16 |
|
T58 |
28 |
|
T34 |
1 |
| false |
654 |
1 |
|
T18 |
3 |
|
T58 |
9 |
|
T83 |
1 |
| true |
448 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1159 |
1 |
|
T18 |
14 |
|
T58 |
10 |
|
T82 |
3 |
| others[1] |
1250 |
1 |
|
T18 |
13 |
|
T58 |
16 |
|
T34 |
1 |
| others[2] |
1256 |
1 |
|
T18 |
11 |
|
T33 |
1 |
|
T58 |
18 |
| others[3] |
2191 |
1 |
|
T18 |
20 |
|
T58 |
31 |
|
T59 |
1 |
| false |
636 |
1 |
|
T18 |
4 |
|
T58 |
12 |
|
T59 |
1 |
| true |
443 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
114 |
1 |
|
T52 |
1 |
|
T143 |
1 |
|
T248 |
1 |
| others[1] |
117 |
1 |
|
T59 |
1 |
|
T238 |
1 |
|
T64 |
7 |
| others[2] |
99 |
1 |
|
T59 |
1 |
|
T64 |
3 |
|
T69 |
8 |
| others[3] |
197 |
1 |
|
T118 |
1 |
|
T139 |
2 |
|
T143 |
1 |
| false |
44 |
1 |
|
T129 |
1 |
|
T395 |
1 |
|
T69 |
2 |
| true |
6364 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T3 |
1 |
|
T19 |
1 |
|
T23 |
1 |
| others[1] |
252 |
1 |
|
T132 |
1 |
|
T393 |
1 |
|
T248 |
1 |
| others[2] |
237 |
1 |
|
T24 |
1 |
|
T53 |
1 |
|
T139 |
1 |
| others[3] |
399 |
1 |
|
T4 |
1 |
|
T52 |
1 |
|
T94 |
1 |
| false |
121 |
1 |
|
T43 |
1 |
|
T64 |
4 |
|
T204 |
1 |
| true |
5716 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1082 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T18 |
10 |
| others[1] |
1070 |
1 |
|
T3 |
1 |
|
T18 |
5 |
|
T58 |
11 |
| others[2] |
1043 |
1 |
|
T18 |
5 |
|
T46 |
1 |
|
T58 |
20 |
| others[3] |
1805 |
1 |
|
T17 |
1 |
|
T18 |
6 |
|
T33 |
1 |
| false |
551 |
1 |
|
T58 |
5 |
|
T82 |
2 |
|
T83 |
2 |
| true |
1384 |
1 |
|
T18 |
36 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
197 |
1 |
|
T43 |
1 |
|
T64 |
10 |
|
T203 |
1 |
| others[1] |
251 |
1 |
|
T19 |
1 |
|
T59 |
1 |
|
T143 |
1 |
| others[2] |
242 |
1 |
|
T392 |
1 |
|
T139 |
1 |
|
T301 |
1 |
| others[3] |
371 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T46 |
1 |
| false |
125 |
1 |
|
T93 |
1 |
|
T43 |
2 |
|
T64 |
4 |
| true |
5749 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
198 |
1 |
|
T4 |
1 |
|
T120 |
1 |
|
T64 |
7 |
| others[1] |
214 |
1 |
|
T52 |
1 |
|
T139 |
1 |
|
T64 |
4 |
| others[2] |
211 |
1 |
|
T59 |
1 |
|
T165 |
1 |
|
T64 |
14 |
| others[3] |
412 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T51 |
1 |
| false |
119 |
1 |
|
T64 |
6 |
|
T69 |
6 |
|
T121 |
4 |
| true |
5781 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1213 |
1 |
|
T18 |
10 |
|
T33 |
1 |
|
T58 |
17 |
| others[1] |
1283 |
1 |
|
T1 |
1 |
|
T18 |
13 |
|
T58 |
9 |
| others[2] |
1209 |
1 |
|
T18 |
14 |
|
T58 |
21 |
|
T5 |
1 |
| others[3] |
2117 |
1 |
|
T18 |
19 |
|
T46 |
1 |
|
T58 |
28 |
| false |
664 |
1 |
|
T18 |
6 |
|
T58 |
12 |
|
T59 |
1 |
| true |
449 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1285 |
1 |
|
T18 |
9 |
|
T58 |
19 |
|
T82 |
4 |
| others[1] |
1221 |
1 |
|
T18 |
12 |
|
T46 |
1 |
|
T58 |
15 |
| others[2] |
1232 |
1 |
|
T18 |
11 |
|
T58 |
17 |
|
T59 |
1 |
| others[3] |
2122 |
1 |
|
T18 |
22 |
|
T33 |
1 |
|
T58 |
31 |
| false |
637 |
1 |
|
T18 |
8 |
|
T58 |
5 |
|
T34 |
1 |
| true |
438 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T116 |
1 |
|
T139 |
1 |
|
T64 |
3 |
| others[1] |
96 |
1 |
|
T59 |
1 |
|
T243 |
1 |
|
T238 |
1 |
| others[2] |
108 |
1 |
|
T52 |
1 |
|
T143 |
1 |
|
T165 |
1 |
| others[3] |
194 |
1 |
|
T1 |
1 |
|
T59 |
1 |
|
T139 |
1 |
| false |
64 |
1 |
|
T248 |
1 |
|
T64 |
3 |
|
T395 |
1 |
| true |
6363 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T2 |
1 |
|
T116 |
1 |
|
T143 |
1 |
| others[1] |
243 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T135 |
1 |
| others[2] |
224 |
1 |
|
T59 |
1 |
|
T392 |
1 |
|
T248 |
1 |
| others[3] |
408 |
1 |
|
T46 |
1 |
|
T94 |
1 |
|
T53 |
1 |
| false |
115 |
1 |
|
T20 |
1 |
|
T52 |
1 |
|
T139 |
1 |
| true |
5721 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1037 |
1 |
|
T2 |
1 |
|
T18 |
6 |
|
T33 |
1 |
| others[1] |
1092 |
1 |
|
T18 |
4 |
|
T20 |
1 |
|
T58 |
17 |
| others[2] |
1112 |
1 |
|
T18 |
9 |
|
T46 |
1 |
|
T58 |
20 |
| others[3] |
1780 |
1 |
|
T17 |
1 |
|
T18 |
11 |
|
T58 |
32 |
| false |
546 |
1 |
|
T18 |
4 |
|
T58 |
8 |
|
T82 |
1 |
| true |
1368 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T18 |
28 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T59 |
1 |
|
T137 |
1 |
|
T143 |
1 |
| others[1] |
225 |
1 |
|
T118 |
1 |
|
T30 |
1 |
|
T248 |
1 |
| others[2] |
258 |
1 |
|
T2 |
1 |
|
T51 |
1 |
|
T52 |
1 |
| others[3] |
394 |
1 |
|
T46 |
1 |
|
T24 |
1 |
|
T132 |
1 |
| false |
117 |
1 |
|
T1 |
1 |
|
T243 |
1 |
|
T359 |
1 |
| true |
5727 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T2 |
1 |
|
T243 |
1 |
|
T64 |
9 |
| others[1] |
244 |
1 |
|
T46 |
1 |
|
T94 |
1 |
|
T64 |
9 |
| others[2] |
220 |
1 |
|
T1 |
1 |
|
T139 |
1 |
|
T248 |
1 |
| others[3] |
365 |
1 |
|
T119 |
1 |
|
T137 |
1 |
|
T64 |
22 |
| false |
119 |
1 |
|
T393 |
1 |
|
T165 |
1 |
|
T238 |
1 |
| true |
5763 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1245 |
1 |
|
T18 |
11 |
|
T58 |
17 |
|
T59 |
1 |
| others[1] |
1263 |
1 |
|
T18 |
14 |
|
T46 |
1 |
|
T58 |
14 |
| others[2] |
1227 |
1 |
|
T18 |
13 |
|
T58 |
16 |
|
T34 |
1 |
| others[3] |
2107 |
1 |
|
T1 |
1 |
|
T18 |
21 |
|
T19 |
1 |
| false |
625 |
1 |
|
T18 |
3 |
|
T33 |
1 |
|
T58 |
10 |
| true |
468 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1276 |
1 |
|
T18 |
14 |
|
T58 |
16 |
|
T34 |
1 |
| others[1] |
1235 |
1 |
|
T18 |
11 |
|
T58 |
14 |
|
T82 |
2 |
| others[2] |
1253 |
1 |
|
T18 |
8 |
|
T58 |
15 |
|
T53 |
1 |
| others[3] |
2111 |
1 |
|
T18 |
23 |
|
T33 |
1 |
|
T58 |
32 |
| false |
623 |
1 |
|
T18 |
6 |
|
T58 |
10 |
|
T82 |
4 |
| true |
437 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
97 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T143 |
1 |
| others[1] |
114 |
1 |
|
T248 |
1 |
|
T239 |
1 |
|
T64 |
6 |
| others[2] |
100 |
1 |
|
T59 |
1 |
|
T139 |
2 |
|
T243 |
1 |
| others[3] |
186 |
1 |
|
T17 |
1 |
|
T59 |
1 |
|
T116 |
1 |
| false |
60 |
1 |
|
T64 |
1 |
|
T65 |
1 |
|
T395 |
1 |
| true |
6378 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T51 |
1 |
|
T59 |
1 |
|
T393 |
1 |
| others[1] |
247 |
1 |
|
T53 |
1 |
|
T118 |
1 |
|
T143 |
1 |
| others[2] |
263 |
1 |
|
T120 |
1 |
|
T119 |
1 |
|
T227 |
1 |
| others[3] |
362 |
1 |
|
T3 |
1 |
|
T139 |
1 |
|
T23 |
1 |
| false |
138 |
1 |
|
T1 |
1 |
|
T24 |
1 |
|
T30 |
1 |
| true |
5690 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1065 |
1 |
|
T18 |
12 |
|
T51 |
1 |
|
T58 |
23 |
| others[1] |
1076 |
1 |
|
T18 |
7 |
|
T19 |
1 |
|
T58 |
21 |
| others[2] |
1077 |
1 |
|
T18 |
7 |
|
T47 |
1 |
|
T58 |
15 |
| others[3] |
1750 |
1 |
|
T1 |
1 |
|
T18 |
13 |
|
T33 |
1 |
| false |
567 |
1 |
|
T18 |
3 |
|
T58 |
7 |
|
T80 |
7 |
| true |
1400 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T118 |
1 |
|
T227 |
1 |
|
T64 |
8 |
| others[1] |
257 |
1 |
|
T46 |
1 |
|
T393 |
1 |
|
T301 |
1 |
| others[2] |
237 |
1 |
|
T24 |
1 |
|
T59 |
1 |
|
T120 |
1 |
| others[3] |
381 |
1 |
|
T1 |
1 |
|
T52 |
1 |
|
T30 |
1 |
| false |
104 |
1 |
|
T51 |
1 |
|
T135 |
1 |
|
T64 |
5 |
| true |
5742 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T46 |
1 |
|
T116 |
1 |
|
T64 |
5 |
| others[1] |
207 |
1 |
|
T137 |
1 |
|
T238 |
1 |
|
T64 |
6 |
| others[2] |
231 |
1 |
|
T392 |
1 |
|
T119 |
1 |
|
T143 |
1 |
| others[3] |
373 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T4 |
1 |
| false |
109 |
1 |
|
T19 |
1 |
|
T132 |
1 |
|
T64 |
6 |
| true |
5806 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1245 |
1 |
|
T18 |
14 |
|
T58 |
20 |
|
T34 |
1 |
| others[1] |
1252 |
1 |
|
T18 |
14 |
|
T58 |
14 |
|
T82 |
3 |
| others[2] |
1227 |
1 |
|
T18 |
13 |
|
T4 |
1 |
|
T33 |
1 |
| others[3] |
2070 |
1 |
|
T18 |
14 |
|
T58 |
21 |
|
T52 |
1 |
| false |
662 |
1 |
|
T18 |
7 |
|
T58 |
11 |
|
T35 |
1 |
| true |
479 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1283 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T18 |
10 |
| others[1] |
1260 |
1 |
|
T18 |
10 |
|
T33 |
1 |
|
T58 |
22 |
| others[2] |
1245 |
1 |
|
T18 |
20 |
|
T58 |
13 |
|
T82 |
3 |
| others[3] |
2114 |
1 |
|
T18 |
13 |
|
T58 |
32 |
|
T82 |
2 |
| false |
596 |
1 |
|
T18 |
9 |
|
T58 |
6 |
|
T59 |
2 |
| true |
437 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T4 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |