Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
97 |
1 |
|
T143 |
1 |
|
T248 |
1 |
|
T64 |
3 |
| others[1] |
105 |
1 |
|
T393 |
1 |
|
T116 |
1 |
|
T139 |
1 |
| others[2] |
101 |
1 |
|
T143 |
1 |
|
T248 |
1 |
|
T64 |
6 |
| others[3] |
195 |
1 |
|
T52 |
1 |
|
T59 |
1 |
|
T139 |
1 |
| false |
47 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T59 |
1 |
| true |
6390 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T20 |
1 |
|
T93 |
1 |
|
T248 |
1 |
| others[1] |
205 |
1 |
|
T46 |
1 |
|
T52 |
1 |
|
T59 |
1 |
| others[2] |
246 |
1 |
|
T17 |
1 |
|
T118 |
1 |
|
T137 |
1 |
| others[3] |
420 |
1 |
|
T3 |
1 |
|
T51 |
1 |
|
T143 |
1 |
| false |
110 |
1 |
|
T59 |
1 |
|
T248 |
1 |
|
T64 |
8 |
| true |
5735 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1019 |
1 |
|
T17 |
1 |
|
T18 |
2 |
|
T58 |
20 |
| others[1] |
1041 |
1 |
|
T18 |
4 |
|
T33 |
1 |
|
T58 |
14 |
| others[2] |
1093 |
1 |
|
T18 |
6 |
|
T47 |
1 |
|
T58 |
20 |
| others[3] |
1843 |
1 |
|
T18 |
13 |
|
T20 |
1 |
|
T58 |
28 |
| false |
549 |
1 |
|
T18 |
3 |
|
T46 |
1 |
|
T58 |
5 |
| true |
1390 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T132 |
1 |
|
T116 |
1 |
|
T93 |
1 |
| others[1] |
226 |
1 |
|
T46 |
1 |
|
T139 |
1 |
|
T135 |
1 |
| others[2] |
210 |
1 |
|
T64 |
7 |
|
T394 |
1 |
|
T69 |
7 |
| others[3] |
408 |
1 |
|
T17 |
1 |
|
T4 |
1 |
|
T19 |
1 |
| false |
130 |
1 |
|
T393 |
1 |
|
T30 |
1 |
|
T23 |
1 |
| true |
5725 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T94 |
1 |
|
T139 |
1 |
|
T239 |
1 |
| others[1] |
200 |
1 |
|
T4 |
1 |
|
T59 |
1 |
|
T143 |
1 |
| others[2] |
235 |
1 |
|
T132 |
1 |
|
T64 |
14 |
|
T65 |
1 |
| others[3] |
378 |
1 |
|
T17 |
1 |
|
T51 |
1 |
|
T165 |
1 |
| false |
130 |
1 |
|
T64 |
3 |
|
T69 |
6 |
|
T121 |
7 |
| true |
5776 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1252 |
1 |
|
T18 |
15 |
|
T58 |
16 |
|
T392 |
1 |
| others[1] |
1236 |
1 |
|
T18 |
7 |
|
T33 |
1 |
|
T58 |
20 |
| others[2] |
1270 |
1 |
|
T18 |
13 |
|
T58 |
15 |
|
T82 |
3 |
| others[3] |
2107 |
1 |
|
T18 |
23 |
|
T58 |
24 |
|
T34 |
1 |
| false |
618 |
1 |
|
T18 |
4 |
|
T58 |
12 |
|
T81 |
6 |
| true |
452 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1246 |
1 |
|
T18 |
17 |
|
T58 |
16 |
|
T34 |
1 |
| others[1] |
1270 |
1 |
|
T18 |
9 |
|
T58 |
24 |
|
T82 |
5 |
| others[2] |
1187 |
1 |
|
T18 |
9 |
|
T46 |
1 |
|
T58 |
9 |
| others[3] |
2117 |
1 |
|
T3 |
1 |
|
T18 |
21 |
|
T33 |
1 |
| false |
669 |
1 |
|
T18 |
6 |
|
T58 |
8 |
|
T83 |
1 |
| true |
446 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T137 |
1 |
|
T64 |
7 |
|
T65 |
1 |
| others[1] |
115 |
1 |
|
T139 |
1 |
|
T238 |
1 |
|
T64 |
6 |
| others[2] |
97 |
1 |
|
T132 |
1 |
|
T139 |
1 |
|
T64 |
7 |
| others[3] |
170 |
1 |
|
T52 |
1 |
|
T59 |
2 |
|
T143 |
2 |
| false |
51 |
1 |
|
T248 |
1 |
|
T239 |
1 |
|
T64 |
2 |
| true |
6395 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T94 |
1 |
|
T139 |
1 |
|
T143 |
1 |
| others[1] |
248 |
1 |
|
T3 |
1 |
|
T132 |
1 |
|
T120 |
1 |
| others[2] |
246 |
1 |
|
T19 |
1 |
|
T53 |
1 |
|
T227 |
1 |
| others[3] |
393 |
1 |
|
T46 |
1 |
|
T24 |
1 |
|
T393 |
1 |
| false |
157 |
1 |
|
T135 |
1 |
|
T239 |
1 |
|
T64 |
10 |
| true |
5655 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1058 |
1 |
|
T3 |
1 |
|
T18 |
2 |
|
T58 |
14 |
| others[1] |
1087 |
1 |
|
T18 |
5 |
|
T46 |
1 |
|
T47 |
1 |
| others[2] |
1039 |
1 |
|
T2 |
1 |
|
T18 |
2 |
|
T51 |
1 |
| others[3] |
1805 |
1 |
|
T18 |
7 |
|
T19 |
1 |
|
T24 |
1 |
| false |
555 |
1 |
|
T18 |
1 |
|
T58 |
14 |
|
T83 |
1 |
| true |
1391 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T18 |
45 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T118 |
1 |
|
T23 |
1 |
|
T243 |
1 |
| others[1] |
223 |
1 |
|
T4 |
1 |
|
T94 |
1 |
|
T143 |
1 |
| others[2] |
234 |
1 |
|
T52 |
1 |
|
T120 |
1 |
|
T139 |
1 |
| others[3] |
387 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T19 |
1 |
| false |
120 |
1 |
|
T132 |
1 |
|
T137 |
1 |
|
T93 |
1 |
| true |
5730 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T17 |
1 |
|
T139 |
2 |
|
T239 |
1 |
| others[1] |
274 |
1 |
|
T120 |
1 |
|
T118 |
1 |
|
T248 |
1 |
| others[2] |
211 |
1 |
|
T4 |
1 |
|
T52 |
1 |
|
T165 |
1 |
| others[3] |
340 |
1 |
|
T51 |
1 |
|
T143 |
1 |
|
T243 |
1 |
| false |
130 |
1 |
|
T2 |
1 |
|
T59 |
1 |
|
T143 |
1 |
| true |
5765 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1265 |
1 |
|
T18 |
16 |
|
T58 |
28 |
|
T94 |
1 |
| others[1] |
1262 |
1 |
|
T18 |
13 |
|
T58 |
15 |
|
T82 |
2 |
| others[2] |
1226 |
1 |
|
T18 |
15 |
|
T58 |
15 |
|
T34 |
1 |
| others[3] |
2037 |
1 |
|
T18 |
11 |
|
T33 |
1 |
|
T58 |
23 |
| false |
685 |
1 |
|
T18 |
7 |
|
T58 |
6 |
|
T82 |
2 |
| true |
460 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1277 |
1 |
|
T18 |
11 |
|
T58 |
20 |
|
T59 |
1 |
| others[1] |
1212 |
1 |
|
T1 |
1 |
|
T18 |
9 |
|
T58 |
14 |
| others[2] |
1248 |
1 |
|
T18 |
13 |
|
T58 |
20 |
|
T59 |
1 |
| others[3] |
2108 |
1 |
|
T18 |
21 |
|
T33 |
1 |
|
T58 |
28 |
| false |
647 |
1 |
|
T18 |
8 |
|
T58 |
5 |
|
T82 |
1 |
| true |
443 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
98 |
1 |
|
T139 |
1 |
|
T143 |
1 |
|
T64 |
4 |
| others[1] |
89 |
1 |
|
T137 |
1 |
|
T64 |
6 |
|
T65 |
1 |
| others[2] |
97 |
1 |
|
T238 |
1 |
|
T64 |
1 |
|
T69 |
8 |
| others[3] |
189 |
1 |
|
T59 |
2 |
|
T139 |
1 |
|
T143 |
1 |
| false |
69 |
1 |
|
T2 |
1 |
|
T248 |
1 |
|
T395 |
1 |
| true |
6393 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T19 |
1 |
|
T137 |
1 |
|
T25 |
1 |
| others[1] |
239 |
1 |
|
T51 |
1 |
|
T52 |
1 |
|
T120 |
1 |
| others[2] |
234 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T238 |
1 |
| others[3] |
419 |
1 |
|
T94 |
1 |
|
T392 |
1 |
|
T116 |
1 |
| false |
127 |
1 |
|
T359 |
1 |
|
T64 |
5 |
|
T69 |
7 |
| true |
5681 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
996 |
1 |
|
T18 |
4 |
|
T4 |
1 |
|
T58 |
18 |
| others[1] |
1074 |
1 |
|
T18 |
10 |
|
T19 |
1 |
|
T58 |
14 |
| others[2] |
1081 |
1 |
|
T18 |
4 |
|
T33 |
1 |
|
T47 |
1 |
| others[3] |
1792 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T18 |
10 |
| false |
564 |
1 |
|
T18 |
1 |
|
T58 |
11 |
|
T81 |
3 |
| true |
1428 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T18 |
33 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T59 |
1 |
|
T132 |
1 |
|
T393 |
1 |
| others[1] |
213 |
1 |
|
T17 |
1 |
|
T20 |
1 |
|
T24 |
1 |
| others[2] |
218 |
1 |
|
T118 |
1 |
|
T165 |
1 |
|
T135 |
1 |
| others[3] |
429 |
1 |
|
T19 |
1 |
|
T51 |
1 |
|
T243 |
1 |
| false |
112 |
1 |
|
T139 |
1 |
|
T143 |
1 |
|
T64 |
4 |
| true |
5734 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T59 |
1 |
|
T139 |
1 |
|
T64 |
7 |
| others[1] |
215 |
1 |
|
T143 |
1 |
|
T165 |
1 |
|
T64 |
14 |
| others[2] |
227 |
1 |
|
T132 |
1 |
|
T248 |
1 |
|
T238 |
1 |
| others[3] |
385 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T143 |
1 |
| false |
111 |
1 |
|
T51 |
1 |
|
T94 |
1 |
|
T116 |
1 |
| true |
5773 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1229 |
1 |
|
T18 |
10 |
|
T58 |
15 |
|
T34 |
1 |
| others[1] |
1214 |
1 |
|
T18 |
6 |
|
T58 |
17 |
|
T82 |
2 |
| others[2] |
1230 |
1 |
|
T18 |
10 |
|
T33 |
1 |
|
T58 |
19 |
| others[3] |
2127 |
1 |
|
T18 |
31 |
|
T19 |
1 |
|
T58 |
24 |
| false |
675 |
1 |
|
T18 |
5 |
|
T58 |
12 |
|
T82 |
1 |
| true |
460 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1207 |
1 |
|
T18 |
8 |
|
T46 |
1 |
|
T58 |
17 |
| others[1] |
1252 |
1 |
|
T18 |
11 |
|
T58 |
20 |
|
T82 |
3 |
| others[2] |
1257 |
1 |
|
T18 |
18 |
|
T33 |
1 |
|
T58 |
19 |
| others[3] |
2140 |
1 |
|
T18 |
16 |
|
T58 |
23 |
|
T82 |
3 |
| false |
640 |
1 |
|
T18 |
9 |
|
T58 |
8 |
|
T34 |
1 |
| true |
439 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
123 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T132 |
1 |
| others[1] |
107 |
1 |
|
T139 |
2 |
|
T64 |
8 |
|
T65 |
1 |
| others[2] |
107 |
1 |
|
T59 |
1 |
|
T64 |
4 |
|
T395 |
1 |
| others[3] |
176 |
1 |
|
T4 |
1 |
|
T59 |
1 |
|
T143 |
1 |
| false |
60 |
1 |
|
T248 |
1 |
|
T64 |
2 |
|
T69 |
2 |
| true |
6362 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
245 |
1 |
|
T17 |
1 |
|
T143 |
1 |
|
T243 |
1 |
| others[1] |
257 |
1 |
|
T30 |
1 |
|
T25 |
1 |
|
T248 |
1 |
| others[2] |
242 |
1 |
|
T3 |
1 |
|
T299 |
1 |
|
T64 |
11 |
| others[3] |
396 |
1 |
|
T119 |
1 |
|
T143 |
1 |
|
T23 |
1 |
| false |
120 |
1 |
|
T2 |
1 |
|
T19 |
1 |
|
T52 |
1 |
| true |
5675 |
1 |
|
T1 |
1 |
|
T18 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1078 |
1 |
|
T3 |
1 |
|
T18 |
6 |
|
T24 |
1 |
| others[1] |
1070 |
1 |
|
T18 |
6 |
|
T19 |
1 |
|
T46 |
1 |
| others[2] |
1120 |
1 |
|
T18 |
2 |
|
T33 |
1 |
|
T58 |
18 |
| others[3] |
1764 |
1 |
|
T18 |
16 |
|
T4 |
1 |
|
T51 |
1 |
| false |
523 |
1 |
|
T18 |
2 |
|
T58 |
10 |
|
T59 |
1 |
| true |
1380 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T392 |
1 |
|
T139 |
1 |
|
T243 |
1 |
| others[1] |
231 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T237 |
1 |
| others[2] |
225 |
1 |
|
T46 |
1 |
|
T165 |
1 |
|
T135 |
1 |
| others[3] |
423 |
1 |
|
T19 |
1 |
|
T24 |
1 |
|
T393 |
1 |
| false |
101 |
1 |
|
T53 |
1 |
|
T64 |
5 |
|
T44 |
1 |
| true |
5721 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
264 |
1 |
|
T4 |
1 |
|
T393 |
1 |
|
T248 |
1 |
| others[1] |
196 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T64 |
5 |
| others[2] |
234 |
1 |
|
T64 |
12 |
|
T129 |
1 |
|
T395 |
2 |
| others[3] |
377 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T94 |
1 |
| false |
119 |
1 |
|
T51 |
1 |
|
T64 |
3 |
|
T397 |
1 |
| true |
5745 |
1 |
|
T3 |
1 |
|
T18 |
62 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1314 |
1 |
|
T18 |
12 |
|
T58 |
21 |
|
T82 |
3 |
| others[1] |
1224 |
1 |
|
T3 |
1 |
|
T18 |
14 |
|
T58 |
20 |
| others[2] |
1199 |
1 |
|
T18 |
7 |
|
T58 |
14 |
|
T83 |
2 |
| others[3] |
2116 |
1 |
|
T18 |
25 |
|
T33 |
1 |
|
T58 |
25 |
| false |
626 |
1 |
|
T18 |
4 |
|
T58 |
7 |
|
T82 |
3 |
| true |
456 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1215 |
1 |
|
T18 |
10 |
|
T58 |
14 |
|
T34 |
1 |
| others[1] |
1294 |
1 |
|
T18 |
16 |
|
T58 |
17 |
|
T59 |
2 |
| others[2] |
1289 |
1 |
|
T18 |
13 |
|
T33 |
1 |
|
T58 |
18 |
| others[3] |
2084 |
1 |
|
T18 |
17 |
|
T46 |
1 |
|
T58 |
29 |
| false |
612 |
1 |
|
T18 |
6 |
|
T58 |
9 |
|
T81 |
7 |
| true |
441 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
119 |
1 |
|
T118 |
1 |
|
T139 |
1 |
|
T143 |
1 |
| others[1] |
110 |
1 |
|
T248 |
1 |
|
T64 |
5 |
|
T65 |
1 |
| others[2] |
111 |
1 |
|
T238 |
1 |
|
T64 |
5 |
|
T69 |
3 |
| others[3] |
166 |
1 |
|
T59 |
1 |
|
T248 |
1 |
|
T64 |
4 |
| false |
51 |
1 |
|
T59 |
1 |
|
T139 |
1 |
|
T143 |
1 |
| true |
6378 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
254 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T20 |
1 |
| others[1] |
244 |
1 |
|
T118 |
1 |
|
T143 |
1 |
|
T23 |
1 |
| others[2] |
221 |
1 |
|
T4 |
1 |
|
T53 |
1 |
|
T248 |
1 |
| others[3] |
418 |
1 |
|
T2 |
1 |
|
T51 |
1 |
|
T120 |
1 |
| false |
109 |
1 |
|
T25 |
1 |
|
T64 |
3 |
|
T69 |
6 |
| true |
5689 |
1 |
|
T17 |
1 |
|
T18 |
62 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1042 |
1 |
|
T18 |
4 |
|
T24 |
1 |
|
T58 |
15 |
| others[1] |
1097 |
1 |
|
T18 |
4 |
|
T58 |
15 |
|
T132 |
1 |
| others[2] |
1044 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T18 |
5 |
| others[3] |
1772 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T18 |
13 |
| false |
580 |
1 |
|
T18 |
2 |
|
T58 |
6 |
|
T82 |
1 |
| true |
1400 |
1 |
|
T18 |
34 |
|
T19 |
1 |
|
T46 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |