Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T4 |
1 |
|
T392 |
1 |
|
T116 |
1 |
| others[1] |
270 |
1 |
|
T17 |
1 |
|
T46 |
1 |
|
T132 |
1 |
| others[2] |
235 |
1 |
|
T23 |
1 |
|
T301 |
1 |
|
T64 |
12 |
| others[3] |
373 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T20 |
1 |
| false |
115 |
1 |
|
T118 |
1 |
|
T119 |
1 |
|
T64 |
4 |
| true |
5703 |
1 |
|
T3 |
1 |
|
T18 |
62 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T52 |
1 |
|
T94 |
1 |
|
T139 |
1 |
| others[1] |
224 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
| others[2] |
214 |
1 |
|
T17 |
1 |
|
T59 |
1 |
|
T393 |
1 |
| others[3] |
362 |
1 |
|
T51 |
1 |
|
T59 |
1 |
|
T392 |
1 |
| false |
129 |
1 |
|
T64 |
5 |
|
T69 |
5 |
|
T6 |
1 |
| true |
5774 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1279 |
1 |
|
T18 |
15 |
|
T58 |
19 |
|
T59 |
1 |
| others[1] |
1259 |
1 |
|
T18 |
11 |
|
T58 |
23 |
|
T52 |
1 |
| others[2] |
1204 |
1 |
|
T18 |
6 |
|
T33 |
1 |
|
T58 |
13 |
| others[3] |
2099 |
1 |
|
T18 |
24 |
|
T58 |
26 |
|
T34 |
1 |
| false |
631 |
1 |
|
T18 |
6 |
|
T58 |
6 |
|
T83 |
2 |
| true |
463 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1256 |
1 |
|
T18 |
12 |
|
T58 |
15 |
|
T59 |
1 |
| others[1] |
1270 |
1 |
|
T18 |
14 |
|
T58 |
14 |
|
T83 |
3 |
| others[2] |
1263 |
1 |
|
T18 |
7 |
|
T33 |
1 |
|
T58 |
18 |
| others[3] |
2048 |
1 |
|
T1 |
1 |
|
T18 |
20 |
|
T58 |
28 |
| false |
668 |
1 |
|
T18 |
9 |
|
T58 |
12 |
|
T34 |
1 |
| true |
430 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T59 |
1 |
|
T139 |
1 |
|
T243 |
1 |
| others[1] |
103 |
1 |
|
T393 |
1 |
|
T64 |
3 |
|
T69 |
5 |
| others[2] |
120 |
1 |
|
T139 |
1 |
|
T248 |
1 |
|
T238 |
1 |
| others[3] |
174 |
1 |
|
T19 |
1 |
|
T143 |
1 |
|
T248 |
1 |
| false |
46 |
1 |
|
T59 |
1 |
|
T143 |
1 |
|
T64 |
4 |
| true |
6388 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T24 |
1 |
|
T132 |
1 |
|
T118 |
1 |
| others[1] |
240 |
1 |
|
T2 |
1 |
|
T19 |
1 |
|
T20 |
1 |
| others[2] |
268 |
1 |
|
T46 |
1 |
|
T143 |
1 |
|
T135 |
1 |
| others[3] |
361 |
1 |
|
T51 |
1 |
|
T52 |
1 |
|
T59 |
1 |
| false |
124 |
1 |
|
T237 |
1 |
|
T299 |
1 |
|
T43 |
2 |
| true |
5718 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1019 |
1 |
|
T18 |
7 |
|
T33 |
1 |
|
T58 |
15 |
| others[1] |
1058 |
1 |
|
T18 |
1 |
|
T4 |
1 |
|
T58 |
20 |
| others[2] |
1054 |
1 |
|
T18 |
6 |
|
T58 |
20 |
|
T82 |
2 |
| others[3] |
1826 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T18 |
11 |
| false |
560 |
1 |
|
T18 |
2 |
|
T24 |
1 |
|
T58 |
8 |
| true |
1418 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T18 |
35 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T135 |
1 |
|
T243 |
1 |
|
T64 |
9 |
| others[1] |
219 |
1 |
|
T143 |
2 |
|
T227 |
1 |
|
T359 |
1 |
| others[2] |
228 |
1 |
|
T59 |
1 |
|
T137 |
1 |
|
T165 |
1 |
| others[3] |
372 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T4 |
1 |
| false |
128 |
1 |
|
T24 |
1 |
|
T52 |
1 |
|
T392 |
1 |
| true |
5748 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T139 |
1 |
|
T165 |
1 |
|
T64 |
9 |
| others[1] |
218 |
1 |
|
T2 |
1 |
|
T94 |
1 |
|
T132 |
1 |
| others[2] |
228 |
1 |
|
T59 |
1 |
|
T64 |
6 |
|
T69 |
10 |
| others[3] |
373 |
1 |
|
T17 |
1 |
|
T19 |
1 |
|
T59 |
1 |
| false |
134 |
1 |
|
T64 |
9 |
|
T69 |
8 |
|
T6 |
1 |
| true |
5759 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1174 |
1 |
|
T3 |
1 |
|
T18 |
10 |
|
T58 |
20 |
| others[1] |
1275 |
1 |
|
T18 |
9 |
|
T19 |
1 |
|
T58 |
9 |
| others[2] |
1294 |
1 |
|
T18 |
14 |
|
T58 |
21 |
|
T59 |
1 |
| others[3] |
2138 |
1 |
|
T18 |
18 |
|
T33 |
1 |
|
T58 |
28 |
| false |
595 |
1 |
|
T18 |
11 |
|
T58 |
9 |
|
T82 |
3 |
| true |
459 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1293 |
1 |
|
T18 |
15 |
|
T58 |
21 |
|
T82 |
1 |
| others[1] |
1234 |
1 |
|
T18 |
12 |
|
T33 |
1 |
|
T58 |
14 |
| others[2] |
1246 |
1 |
|
T18 |
8 |
|
T58 |
16 |
|
T83 |
1 |
| others[3] |
2062 |
1 |
|
T18 |
24 |
|
T58 |
24 |
|
T34 |
1 |
| false |
664 |
1 |
|
T18 |
3 |
|
T58 |
12 |
|
T5 |
1 |
| true |
436 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
95 |
1 |
|
T132 |
1 |
|
T393 |
1 |
|
T139 |
1 |
| others[1] |
109 |
1 |
|
T143 |
1 |
|
T238 |
1 |
|
T64 |
5 |
| others[2] |
117 |
1 |
|
T59 |
1 |
|
T137 |
1 |
|
T64 |
3 |
| others[3] |
166 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T51 |
1 |
| false |
49 |
1 |
|
T143 |
1 |
|
T64 |
2 |
|
T395 |
2 |
| true |
6399 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
269 |
1 |
|
T4 |
1 |
|
T59 |
1 |
|
T143 |
1 |
| others[1] |
268 |
1 |
|
T2 |
1 |
|
T46 |
1 |
|
T116 |
1 |
| others[2] |
232 |
1 |
|
T3 |
1 |
|
T25 |
1 |
|
T93 |
1 |
| others[3] |
384 |
1 |
|
T132 |
1 |
|
T53 |
1 |
|
T118 |
1 |
| false |
125 |
1 |
|
T19 |
1 |
|
T30 |
1 |
|
T64 |
5 |
| true |
5657 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1034 |
1 |
|
T18 |
4 |
|
T20 |
1 |
|
T51 |
1 |
| others[1] |
1043 |
1 |
|
T18 |
7 |
|
T19 |
1 |
|
T58 |
15 |
| others[2] |
1068 |
1 |
|
T18 |
7 |
|
T33 |
1 |
|
T47 |
1 |
| others[3] |
1841 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T18 |
9 |
| false |
560 |
1 |
|
T18 |
2 |
|
T24 |
1 |
|
T58 |
5 |
| true |
1389 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T18 |
33 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T2 |
1 |
|
T46 |
1 |
|
T52 |
1 |
| others[1] |
248 |
1 |
|
T1 |
1 |
|
T237 |
1 |
|
T43 |
3 |
| others[2] |
213 |
1 |
|
T94 |
1 |
|
T135 |
1 |
|
T43 |
2 |
| others[3] |
385 |
1 |
|
T17 |
1 |
|
T4 |
1 |
|
T19 |
1 |
| false |
126 |
1 |
|
T393 |
1 |
|
T143 |
1 |
|
T23 |
1 |
| true |
5732 |
1 |
|
T3 |
1 |
|
T18 |
62 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T118 |
1 |
| others[1] |
234 |
1 |
|
T46 |
1 |
|
T59 |
1 |
|
T119 |
1 |
| others[2] |
219 |
1 |
|
T51 |
1 |
|
T59 |
1 |
|
T392 |
1 |
| others[3] |
346 |
1 |
|
T17 |
1 |
|
T132 |
1 |
|
T116 |
1 |
| false |
136 |
1 |
|
T64 |
9 |
|
T69 |
6 |
|
T121 |
3 |
| true |
5759 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1268 |
1 |
|
T18 |
16 |
|
T58 |
14 |
|
T82 |
2 |
| others[1] |
1220 |
1 |
|
T18 |
9 |
|
T58 |
19 |
|
T59 |
1 |
| others[2] |
1232 |
1 |
|
T18 |
9 |
|
T58 |
12 |
|
T82 |
4 |
| others[3] |
2100 |
1 |
|
T18 |
21 |
|
T33 |
1 |
|
T58 |
34 |
| false |
643 |
1 |
|
T18 |
7 |
|
T58 |
8 |
|
T34 |
1 |
| true |
472 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1203 |
1 |
|
T18 |
11 |
|
T58 |
11 |
|
T82 |
2 |
| others[1] |
1265 |
1 |
|
T18 |
10 |
|
T58 |
17 |
|
T59 |
1 |
| others[2] |
1309 |
1 |
|
T3 |
1 |
|
T18 |
13 |
|
T58 |
24 |
| others[3] |
2010 |
1 |
|
T18 |
20 |
|
T33 |
1 |
|
T58 |
25 |
| false |
705 |
1 |
|
T18 |
8 |
|
T58 |
10 |
|
T35 |
1 |
| true |
443 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
115 |
1 |
|
T143 |
1 |
|
T248 |
1 |
|
T64 |
1 |
| others[1] |
101 |
1 |
|
T143 |
1 |
|
T239 |
1 |
|
T64 |
6 |
| others[2] |
95 |
1 |
|
T248 |
1 |
|
T64 |
4 |
|
T395 |
1 |
| others[3] |
172 |
1 |
|
T59 |
2 |
|
T118 |
1 |
|
T139 |
2 |
| false |
62 |
1 |
|
T238 |
1 |
|
T64 |
1 |
|
T395 |
1 |
| true |
6390 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
254 |
1 |
|
T25 |
1 |
|
T359 |
1 |
|
T301 |
1 |
| others[1] |
226 |
1 |
|
T1 |
1 |
|
T137 |
1 |
|
T143 |
1 |
| others[2] |
234 |
1 |
|
T19 |
1 |
|
T52 |
1 |
|
T116 |
1 |
| others[3] |
374 |
1 |
|
T393 |
1 |
|
T30 |
1 |
|
T43 |
1 |
| false |
147 |
1 |
|
T59 |
1 |
|
T118 |
1 |
|
T23 |
1 |
| true |
5700 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1090 |
1 |
|
T17 |
1 |
|
T18 |
1 |
|
T19 |
1 |
| others[1] |
1018 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| others[2] |
1041 |
1 |
|
T18 |
9 |
|
T4 |
1 |
|
T20 |
1 |
| others[3] |
1810 |
1 |
|
T18 |
9 |
|
T58 |
29 |
|
T5 |
2 |
| false |
571 |
1 |
|
T18 |
7 |
|
T24 |
1 |
|
T58 |
13 |
| true |
1405 |
1 |
|
T18 |
30 |
|
T51 |
1 |
|
T52 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T20 |
1 |
|
T393 |
1 |
|
T143 |
1 |
| others[1] |
246 |
1 |
|
T2 |
1 |
|
T248 |
1 |
|
T64 |
11 |
| others[2] |
228 |
1 |
|
T1 |
1 |
|
T19 |
1 |
|
T392 |
1 |
| others[3] |
381 |
1 |
|
T46 |
1 |
|
T94 |
1 |
|
T59 |
1 |
| false |
148 |
1 |
|
T43 |
2 |
|
T238 |
1 |
|
T64 |
4 |
| true |
5690 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T64 |
6 |
|
T69 |
10 |
|
T6 |
2 |
| others[1] |
238 |
1 |
|
T19 |
1 |
|
T46 |
1 |
|
T59 |
1 |
| others[2] |
253 |
1 |
|
T59 |
1 |
|
T120 |
1 |
|
T64 |
14 |
| others[3] |
338 |
1 |
|
T52 |
1 |
|
T119 |
1 |
|
T143 |
1 |
| false |
117 |
1 |
|
T94 |
1 |
|
T64 |
6 |
|
T395 |
1 |
| true |
5761 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1287 |
1 |
|
T18 |
12 |
|
T58 |
14 |
|
T83 |
2 |
| others[1] |
1264 |
1 |
|
T18 |
12 |
|
T33 |
1 |
|
T58 |
13 |
| others[2] |
1251 |
1 |
|
T18 |
15 |
|
T58 |
20 |
|
T82 |
1 |
| others[3] |
2062 |
1 |
|
T17 |
1 |
|
T18 |
18 |
|
T58 |
23 |
| false |
602 |
1 |
|
T18 |
5 |
|
T58 |
17 |
|
T82 |
1 |
| true |
469 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1284 |
1 |
|
T18 |
10 |
|
T58 |
15 |
|
T34 |
1 |
| others[1] |
1258 |
1 |
|
T18 |
16 |
|
T58 |
13 |
|
T82 |
1 |
| others[2] |
1224 |
1 |
|
T18 |
11 |
|
T58 |
16 |
|
T82 |
4 |
| others[3] |
2065 |
1 |
|
T18 |
19 |
|
T33 |
1 |
|
T58 |
36 |
| false |
653 |
1 |
|
T18 |
6 |
|
T58 |
7 |
|
T82 |
1 |
| true |
451 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
120 |
1 |
|
T248 |
1 |
|
T64 |
7 |
|
T69 |
4 |
| others[1] |
93 |
1 |
|
T143 |
1 |
|
T238 |
1 |
|
T64 |
4 |
| others[2] |
109 |
1 |
|
T393 |
1 |
|
T139 |
2 |
|
T143 |
1 |
| others[3] |
184 |
1 |
|
T59 |
2 |
|
T243 |
1 |
|
T248 |
1 |
| false |
38 |
1 |
|
T165 |
1 |
|
T69 |
2 |
|
T398 |
1 |
| true |
6391 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
256 |
1 |
|
T120 |
1 |
|
T30 |
1 |
|
T139 |
1 |
| others[1] |
259 |
1 |
|
T3 |
1 |
|
T93 |
1 |
|
T237 |
1 |
| others[2] |
241 |
1 |
|
T2 |
1 |
|
T19 |
1 |
|
T119 |
1 |
| others[3] |
384 |
1 |
|
T1 |
1 |
|
T46 |
1 |
|
T24 |
1 |
| false |
124 |
1 |
|
T243 |
1 |
|
T64 |
5 |
|
T230 |
1 |
| true |
5671 |
1 |
|
T17 |
1 |
|
T18 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1109 |
1 |
|
T18 |
6 |
|
T58 |
19 |
|
T82 |
4 |
| others[1] |
1055 |
1 |
|
T1 |
1 |
|
T18 |
6 |
|
T33 |
1 |
| others[2] |
1097 |
1 |
|
T18 |
9 |
|
T58 |
19 |
|
T82 |
3 |
| others[3] |
1777 |
1 |
|
T17 |
1 |
|
T18 |
16 |
|
T4 |
1 |
| false |
530 |
1 |
|
T18 |
1 |
|
T58 |
11 |
|
T82 |
2 |
| true |
1367 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T18 |
24 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T20 |
1 |
|
T52 |
1 |
|
T59 |
1 |
| others[1] |
255 |
1 |
|
T51 |
1 |
|
T132 |
1 |
|
T120 |
1 |
| others[2] |
219 |
1 |
|
T139 |
1 |
|
T64 |
16 |
|
T69 |
14 |
| others[3] |
402 |
1 |
|
T17 |
1 |
|
T4 |
1 |
|
T393 |
1 |
| false |
107 |
1 |
|
T116 |
1 |
|
T64 |
2 |
|
T69 |
3 |
| true |
5713 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T143 |
1 |
|
T243 |
1 |
|
T239 |
1 |
| others[1] |
238 |
1 |
|
T4 |
1 |
|
T51 |
1 |
|
T120 |
1 |
| others[2] |
206 |
1 |
|
T64 |
7 |
|
T69 |
5 |
|
T399 |
1 |
| others[3] |
364 |
1 |
|
T392 |
1 |
|
T116 |
1 |
|
T143 |
1 |
| false |
131 |
1 |
|
T52 |
1 |
|
T118 |
1 |
|
T64 |
7 |
| true |
5782 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1275 |
1 |
|
T18 |
12 |
|
T58 |
16 |
|
T59 |
1 |
| others[1] |
1249 |
1 |
|
T18 |
13 |
|
T4 |
1 |
|
T33 |
1 |
| others[2] |
1226 |
1 |
|
T18 |
12 |
|
T58 |
15 |
|
T82 |
3 |
| others[3] |
2043 |
1 |
|
T18 |
21 |
|
T58 |
27 |
|
T82 |
5 |
| false |
686 |
1 |
|
T18 |
4 |
|
T58 |
7 |
|
T59 |
1 |
| true |
456 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |