Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1258 |
1 |
|
T1 |
1 |
|
T18 |
18 |
|
T58 |
14 |
| others[1] |
1247 |
1 |
|
T18 |
11 |
|
T58 |
16 |
|
T34 |
1 |
| others[2] |
1268 |
1 |
|
T18 |
8 |
|
T33 |
1 |
|
T58 |
25 |
| others[3] |
2085 |
1 |
|
T18 |
17 |
|
T58 |
27 |
|
T59 |
1 |
| false |
637 |
1 |
|
T18 |
8 |
|
T58 |
5 |
|
T82 |
2 |
| true |
440 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
95 |
1 |
|
T248 |
1 |
|
T64 |
2 |
|
T69 |
1 |
| others[1] |
121 |
1 |
|
T64 |
3 |
|
T65 |
1 |
|
T394 |
1 |
| others[2] |
116 |
1 |
|
T59 |
1 |
|
T139 |
2 |
|
T248 |
1 |
| others[3] |
162 |
1 |
|
T59 |
1 |
|
T132 |
1 |
|
T143 |
2 |
| false |
78 |
1 |
|
T393 |
1 |
|
T64 |
3 |
|
T69 |
2 |
| true |
6363 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T51 |
1 |
|
T139 |
2 |
|
T299 |
1 |
| others[1] |
250 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T120 |
1 |
| others[2] |
246 |
1 |
|
T17 |
1 |
|
T4 |
1 |
|
T59 |
1 |
| others[3] |
413 |
1 |
|
T116 |
1 |
|
T23 |
1 |
|
T25 |
1 |
| false |
110 |
1 |
|
T132 |
1 |
|
T64 |
5 |
|
T69 |
4 |
| true |
5675 |
1 |
|
T3 |
1 |
|
T18 |
62 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1087 |
1 |
|
T3 |
1 |
|
T18 |
12 |
|
T58 |
19 |
| others[1] |
1090 |
1 |
|
T18 |
7 |
|
T51 |
1 |
|
T58 |
16 |
| others[2] |
1051 |
1 |
|
T18 |
7 |
|
T19 |
1 |
|
T58 |
12 |
| others[3] |
1759 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T18 |
10 |
| false |
562 |
1 |
|
T18 |
4 |
|
T58 |
10 |
|
T82 |
1 |
| true |
1386 |
1 |
|
T17 |
1 |
|
T18 |
22 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T19 |
1 |
|
T53 |
1 |
|
T119 |
1 |
| others[1] |
212 |
1 |
|
T137 |
1 |
|
T93 |
1 |
|
T64 |
9 |
| others[2] |
221 |
1 |
|
T17 |
1 |
|
T46 |
1 |
|
T23 |
1 |
| others[3] |
407 |
1 |
|
T392 |
1 |
|
T118 |
1 |
|
T143 |
1 |
| false |
126 |
1 |
|
T2 |
1 |
|
T20 |
1 |
|
T59 |
1 |
| true |
5742 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T64 |
4 |
|
T69 |
9 |
|
T121 |
12 |
| others[1] |
228 |
1 |
|
T248 |
1 |
|
T64 |
10 |
|
T395 |
1 |
| others[2] |
227 |
1 |
|
T393 |
1 |
|
T137 |
1 |
|
T64 |
14 |
| others[3] |
360 |
1 |
|
T59 |
1 |
|
T139 |
1 |
|
T239 |
1 |
| false |
128 |
1 |
|
T139 |
1 |
|
T248 |
1 |
|
T64 |
3 |
| true |
5783 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1219 |
1 |
|
T18 |
9 |
|
T58 |
16 |
|
T82 |
5 |
| others[1] |
1211 |
1 |
|
T18 |
16 |
|
T58 |
21 |
|
T59 |
1 |
| others[2] |
1266 |
1 |
|
T18 |
12 |
|
T58 |
14 |
|
T59 |
1 |
| others[3] |
2126 |
1 |
|
T18 |
12 |
|
T51 |
1 |
|
T58 |
28 |
| false |
654 |
1 |
|
T18 |
13 |
|
T33 |
1 |
|
T58 |
8 |
| true |
459 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1264 |
1 |
|
T18 |
13 |
|
T58 |
16 |
|
T59 |
1 |
| others[1] |
1263 |
1 |
|
T18 |
19 |
|
T58 |
11 |
|
T82 |
2 |
| others[2] |
1248 |
1 |
|
T18 |
10 |
|
T58 |
15 |
|
T34 |
1 |
| others[3] |
2100 |
1 |
|
T18 |
18 |
|
T33 |
1 |
|
T58 |
35 |
| false |
622 |
1 |
|
T18 |
2 |
|
T58 |
10 |
|
T82 |
1 |
| true |
438 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
112 |
1 |
|
T59 |
1 |
|
T248 |
1 |
|
T64 |
4 |
| others[1] |
109 |
1 |
|
T2 |
1 |
|
T139 |
1 |
|
T248 |
1 |
| others[2] |
106 |
1 |
|
T59 |
1 |
|
T243 |
1 |
|
T239 |
1 |
| others[3] |
168 |
1 |
|
T143 |
1 |
|
T238 |
1 |
|
T64 |
6 |
| false |
54 |
1 |
|
T139 |
1 |
|
T143 |
1 |
|
T64 |
3 |
| true |
6386 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
259 |
1 |
|
T51 |
1 |
|
T119 |
1 |
|
T165 |
1 |
| others[1] |
239 |
1 |
|
T120 |
1 |
|
T25 |
1 |
|
T43 |
1 |
| others[2] |
227 |
1 |
|
T59 |
1 |
|
T143 |
1 |
|
T227 |
1 |
| others[3] |
400 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
| false |
133 |
1 |
|
T64 |
8 |
|
T69 |
5 |
|
T6 |
1 |
| true |
5677 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1065 |
1 |
|
T18 |
2 |
|
T46 |
1 |
|
T51 |
1 |
| others[1] |
1075 |
1 |
|
T1 |
1 |
|
T18 |
5 |
|
T33 |
1 |
| others[2] |
1066 |
1 |
|
T18 |
5 |
|
T20 |
1 |
|
T58 |
20 |
| others[3] |
1789 |
1 |
|
T18 |
5 |
|
T47 |
1 |
|
T58 |
30 |
| false |
586 |
1 |
|
T18 |
5 |
|
T4 |
1 |
|
T58 |
8 |
| true |
1354 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T20 |
1 |
|
T24 |
1 |
|
T120 |
1 |
| others[1] |
218 |
1 |
|
T393 |
1 |
|
T227 |
1 |
|
T238 |
1 |
| others[2] |
231 |
1 |
|
T52 |
1 |
|
T59 |
1 |
|
T143 |
1 |
| others[3] |
370 |
1 |
|
T17 |
1 |
|
T19 |
1 |
|
T46 |
1 |
| false |
122 |
1 |
|
T59 |
1 |
|
T64 |
4 |
|
T69 |
6 |
| true |
5753 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T119 |
1 |
|
T143 |
1 |
|
T64 |
13 |
| others[1] |
225 |
1 |
|
T52 |
1 |
|
T64 |
7 |
|
T69 |
9 |
| others[2] |
212 |
1 |
|
T4 |
1 |
|
T139 |
1 |
|
T64 |
4 |
| others[3] |
353 |
1 |
|
T2 |
1 |
|
T59 |
1 |
|
T118 |
1 |
| false |
122 |
1 |
|
T51 |
1 |
|
T64 |
6 |
|
T69 |
8 |
| true |
5798 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1143 |
1 |
|
T18 |
12 |
|
T33 |
1 |
|
T58 |
16 |
| others[1] |
1227 |
1 |
|
T18 |
9 |
|
T58 |
16 |
|
T82 |
1 |
| others[2] |
1302 |
1 |
|
T18 |
14 |
|
T58 |
17 |
|
T59 |
1 |
| others[3] |
2130 |
1 |
|
T18 |
23 |
|
T58 |
26 |
|
T59 |
1 |
| false |
685 |
1 |
|
T18 |
4 |
|
T58 |
12 |
|
T82 |
1 |
| true |
448 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1209 |
1 |
|
T18 |
8 |
|
T58 |
14 |
|
T82 |
3 |
| others[1] |
1266 |
1 |
|
T18 |
6 |
|
T58 |
18 |
|
T34 |
1 |
| others[2] |
1298 |
1 |
|
T18 |
15 |
|
T58 |
14 |
|
T59 |
1 |
| others[3] |
2037 |
1 |
|
T18 |
26 |
|
T33 |
1 |
|
T58 |
33 |
| false |
685 |
1 |
|
T18 |
7 |
|
T46 |
1 |
|
T58 |
8 |
| true |
440 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
99 |
1 |
|
T116 |
1 |
|
T64 |
3 |
|
T65 |
1 |
| others[1] |
98 |
1 |
|
T118 |
1 |
|
T139 |
2 |
|
T143 |
1 |
| others[2] |
118 |
1 |
|
T59 |
1 |
|
T64 |
3 |
|
T395 |
2 |
| others[3] |
176 |
1 |
|
T132 |
1 |
|
T143 |
1 |
|
T248 |
1 |
| false |
67 |
1 |
|
T59 |
1 |
|
T248 |
1 |
|
T64 |
2 |
| true |
6377 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T4 |
1 |
|
T46 |
1 |
|
T393 |
1 |
| others[1] |
218 |
1 |
|
T24 |
1 |
|
T132 |
1 |
|
T139 |
1 |
| others[2] |
252 |
1 |
|
T51 |
1 |
|
T243 |
1 |
|
T301 |
1 |
| others[3] |
383 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T19 |
1 |
| false |
133 |
1 |
|
T2 |
1 |
|
T52 |
1 |
|
T53 |
1 |
| true |
5731 |
1 |
|
T1 |
1 |
|
T18 |
62 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1130 |
1 |
|
T18 |
3 |
|
T58 |
20 |
|
T94 |
1 |
| others[1] |
1065 |
1 |
|
T18 |
3 |
|
T33 |
1 |
|
T58 |
26 |
| others[2] |
1087 |
1 |
|
T1 |
1 |
|
T18 |
12 |
|
T4 |
1 |
| others[3] |
1766 |
1 |
|
T17 |
1 |
|
T18 |
6 |
|
T19 |
1 |
| false |
513 |
1 |
|
T18 |
3 |
|
T58 |
6 |
|
T59 |
1 |
| true |
1374 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T18 |
35 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T19 |
1 |
|
T53 |
1 |
|
T227 |
1 |
| others[1] |
239 |
1 |
|
T392 |
1 |
|
T139 |
1 |
|
T301 |
1 |
| others[2] |
211 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T51 |
1 |
| others[3] |
375 |
1 |
|
T135 |
1 |
|
T64 |
18 |
|
T205 |
1 |
| false |
114 |
1 |
|
T1 |
1 |
|
T52 |
1 |
|
T143 |
1 |
| true |
5767 |
1 |
|
T3 |
1 |
|
T18 |
62 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T139 |
1 |
|
T248 |
1 |
|
T239 |
1 |
| others[1] |
243 |
1 |
|
T1 |
1 |
|
T51 |
1 |
|
T393 |
1 |
| others[2] |
207 |
1 |
|
T17 |
1 |
|
T64 |
13 |
|
T69 |
6 |
| others[3] |
381 |
1 |
|
T4 |
1 |
|
T46 |
1 |
|
T139 |
1 |
| false |
122 |
1 |
|
T52 |
1 |
|
T132 |
1 |
|
T137 |
1 |
| true |
5762 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T18 |
62 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1223 |
1 |
|
T18 |
10 |
|
T58 |
16 |
|
T82 |
1 |
| others[1] |
1308 |
1 |
|
T18 |
11 |
|
T46 |
1 |
|
T58 |
22 |
| others[2] |
1188 |
1 |
|
T18 |
18 |
|
T58 |
17 |
|
T34 |
1 |
| others[3] |
2085 |
1 |
|
T18 |
19 |
|
T33 |
1 |
|
T58 |
23 |
| false |
666 |
1 |
|
T18 |
4 |
|
T58 |
9 |
|
T59 |
1 |
| true |
465 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1281 |
1 |
|
T18 |
8 |
|
T58 |
16 |
|
T82 |
2 |
| others[1] |
1217 |
1 |
|
T18 |
13 |
|
T33 |
1 |
|
T58 |
10 |
| others[2] |
1210 |
1 |
|
T1 |
1 |
|
T18 |
15 |
|
T46 |
1 |
| others[3] |
2119 |
1 |
|
T18 |
18 |
|
T58 |
32 |
|
T34 |
1 |
| false |
665 |
1 |
|
T18 |
8 |
|
T58 |
11 |
|
T82 |
1 |
| true |
443 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T64 |
3 |
|
T121 |
5 |
|
T145 |
3 |
| others[1] |
118 |
1 |
|
T59 |
1 |
|
T139 |
1 |
|
T64 |
5 |
| others[2] |
112 |
1 |
|
T118 |
1 |
|
T139 |
1 |
|
T248 |
1 |
| others[3] |
215 |
1 |
|
T143 |
2 |
|
T238 |
1 |
|
T64 |
12 |
| false |
63 |
1 |
|
T59 |
1 |
|
T165 |
1 |
|
T248 |
1 |
| true |
6324 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
258 |
1 |
|
T3 |
1 |
|
T393 |
1 |
|
T299 |
1 |
| others[1] |
229 |
1 |
|
T20 |
1 |
|
T46 |
1 |
|
T239 |
1 |
| others[2] |
267 |
1 |
|
T2 |
1 |
|
T24 |
1 |
|
T94 |
1 |
| others[3] |
428 |
1 |
|
T1 |
1 |
|
T17 |
1 |
|
T4 |
1 |
| false |
107 |
1 |
|
T93 |
1 |
|
T248 |
1 |
|
T64 |
6 |
| true |
5646 |
1 |
|
T18 |
62 |
|
T33 |
1 |
|
T51 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1055 |
1 |
|
T18 |
4 |
|
T58 |
17 |
|
T82 |
3 |
| others[1] |
1028 |
1 |
|
T18 |
9 |
|
T4 |
1 |
|
T33 |
1 |
| others[2] |
1098 |
1 |
|
T18 |
4 |
|
T47 |
1 |
|
T58 |
14 |
| others[3] |
1849 |
1 |
|
T17 |
1 |
|
T18 |
11 |
|
T20 |
1 |
| false |
528 |
1 |
|
T18 |
2 |
|
T58 |
12 |
|
T68 |
1 |
| true |
1377 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T135 |
1 |
|
T43 |
1 |
|
T64 |
9 |
| others[1] |
266 |
1 |
|
T20 |
1 |
|
T51 |
1 |
|
T64 |
12 |
| others[2] |
260 |
1 |
|
T139 |
1 |
|
T143 |
1 |
|
T23 |
1 |
| others[3] |
381 |
1 |
|
T4 |
1 |
|
T46 |
1 |
|
T52 |
1 |
| false |
112 |
1 |
|
T19 |
1 |
|
T24 |
1 |
|
T392 |
1 |
| true |
5692 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T59 |
1 |
|
T139 |
1 |
|
T64 |
8 |
| others[1] |
219 |
1 |
|
T52 |
1 |
|
T116 |
1 |
|
T64 |
9 |
| others[2] |
238 |
1 |
|
T17 |
1 |
|
T59 |
1 |
|
T143 |
1 |
| others[3] |
393 |
1 |
|
T132 |
1 |
|
T392 |
1 |
|
T143 |
1 |
| false |
133 |
1 |
|
T4 |
1 |
|
T118 |
1 |
|
T64 |
5 |
| true |
5740 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1204 |
1 |
|
T18 |
7 |
|
T46 |
1 |
|
T58 |
17 |
| others[1] |
1205 |
1 |
|
T18 |
13 |
|
T58 |
12 |
|
T59 |
1 |
| others[2] |
1254 |
1 |
|
T18 |
8 |
|
T58 |
10 |
|
T132 |
1 |
| others[3] |
2146 |
1 |
|
T18 |
26 |
|
T33 |
1 |
|
T58 |
32 |
| false |
659 |
1 |
|
T18 |
8 |
|
T58 |
16 |
|
T34 |
1 |
| true |
467 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7 |
1 |
|
T9 |
1 |
|
T196 |
1 |
|
T400 |
1 |
| others[1] |
8 |
1 |
|
T401 |
1 |
|
T201 |
1 |
|
T402 |
1 |
| others[2] |
7 |
1 |
|
T174 |
1 |
|
T156 |
1 |
|
T403 |
1 |
| others[3] |
13 |
1 |
|
T193 |
1 |
|
T195 |
1 |
|
T186 |
1 |
| false |
1 |
1 |
|
T404 |
1 |
|
- |
- |
|
- |
- |
| true |
38 |
1 |
|
T105 |
1 |
|
T173 |
1 |
|
T194 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1 |
1 |
|
T405 |
1 |
|
- |
- |
|
- |
- |
| others[1] |
2 |
1 |
|
T15 |
1 |
|
T406 |
1 |
|
- |
- |
| others[2] |
3 |
1 |
|
T407 |
1 |
|
T408 |
1 |
|
T409 |
1 |
| others[3] |
2 |
1 |
|
T410 |
1 |
|
T411 |
1 |
|
- |
- |
| false |
9 |
1 |
|
T29 |
1 |
|
T37 |
1 |
|
T412 |
1 |
| true |
30 |
1 |
|
T21 |
1 |
|
T48 |
1 |
|
T413 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
3 |
1 |
|
T21 |
1 |
|
T29 |
1 |
|
T414 |
1 |
| others[1] |
3 |
1 |
|
T406 |
1 |
|
T415 |
1 |
|
T416 |
1 |
| others[2] |
6 |
1 |
|
T157 |
1 |
|
T412 |
1 |
|
T407 |
1 |
| others[3] |
7 |
1 |
|
T413 |
1 |
|
T417 |
1 |
|
T349 |
1 |
| false |
6 |
1 |
|
T15 |
1 |
|
T418 |
1 |
|
T268 |
1 |
| true |
22 |
1 |
|
T37 |
1 |
|
T48 |
1 |
|
T140 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |