Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10981 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T46 |
1 |
| others[1] |
841 |
1 |
|
T1 |
1 |
|
T58 |
13 |
|
T78 |
2 |
| others[2] |
801 |
1 |
|
T58 |
23 |
|
T34 |
1 |
|
T78 |
1 |
| others[3] |
1293 |
1 |
|
T33 |
1 |
|
T58 |
30 |
|
T59 |
1 |
| false |
379 |
1 |
|
T58 |
5 |
|
T82 |
1 |
|
T167 |
1 |
| true |
552 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2561 |
1 |
|
T16 |
9 |
|
T18 |
15 |
|
T33 |
1 |
| others[1] |
2524 |
1 |
|
T1 |
1 |
|
T16 |
14 |
|
T18 |
15 |
| others[2] |
2541 |
1 |
|
T16 |
14 |
|
T17 |
1 |
|
T18 |
11 |
| others[3] |
4361 |
1 |
|
T16 |
21 |
|
T18 |
17 |
|
T4 |
1 |
| false |
1297 |
1 |
|
T16 |
9 |
|
T18 |
4 |
|
T58 |
11 |
| true |
1563 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10406 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T52 |
1 |
| others[1] |
254 |
1 |
|
T46 |
1 |
|
T33 |
1 |
|
T34 |
1 |
| others[2] |
285 |
1 |
|
T4 |
1 |
|
T24 |
1 |
|
T132 |
1 |
| others[3] |
498 |
1 |
|
T120 |
1 |
|
T118 |
1 |
|
T79 |
1 |
| false |
144 |
1 |
|
T17 |
1 |
|
T78 |
1 |
|
T53 |
1 |
| true |
3260 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10672 |
1 |
|
T16 |
67 |
|
T17 |
1 |
|
T18 |
62 |
| others[1] |
456 |
1 |
|
T58 |
11 |
|
T52 |
1 |
|
T53 |
1 |
| others[2] |
461 |
1 |
|
T3 |
1 |
|
T58 |
9 |
|
T59 |
1 |
| others[3] |
766 |
1 |
|
T2 |
1 |
|
T33 |
1 |
|
T58 |
13 |
| false |
233 |
1 |
|
T1 |
1 |
|
T58 |
3 |
|
T59 |
1 |
| true |
2259 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10423 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T59 |
1 |
| others[1] |
249 |
1 |
|
T2 |
1 |
|
T94 |
1 |
|
T118 |
1 |
| others[2] |
270 |
1 |
|
T51 |
1 |
|
T137 |
1 |
|
T237 |
1 |
| others[3] |
453 |
1 |
|
T46 |
1 |
|
T133 |
1 |
|
T143 |
1 |
| false |
132 |
1 |
|
T20 |
1 |
|
T34 |
1 |
|
T64 |
5 |
| true |
3320 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10426 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T19 |
1 |
| others[1] |
254 |
1 |
|
T4 |
1 |
|
T34 |
1 |
|
T59 |
1 |
| others[2] |
237 |
1 |
|
T51 |
1 |
|
T392 |
1 |
|
T116 |
1 |
| others[3] |
461 |
1 |
|
T1 |
1 |
|
T94 |
1 |
|
T120 |
1 |
| false |
114 |
1 |
|
T64 |
6 |
|
T69 |
4 |
|
T121 |
1 |
| true |
3355 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10999 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T58 |
23 |
| others[1] |
805 |
1 |
|
T58 |
8 |
|
T59 |
1 |
|
T78 |
1 |
| others[2] |
821 |
1 |
|
T33 |
1 |
|
T58 |
20 |
|
T34 |
1 |
| others[3] |
1288 |
1 |
|
T58 |
26 |
|
T78 |
2 |
|
T82 |
3 |
| false |
388 |
1 |
|
T58 |
10 |
|
T78 |
1 |
|
T82 |
1 |
| true |
546 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10964 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T58 |
16 |
| others[1] |
814 |
1 |
|
T46 |
1 |
|
T33 |
1 |
|
T58 |
12 |
| others[2] |
754 |
1 |
|
T51 |
1 |
|
T58 |
19 |
|
T82 |
1 |
| others[3] |
1335 |
1 |
|
T58 |
35 |
|
T34 |
1 |
|
T78 |
3 |
| false |
401 |
1 |
|
T58 |
5 |
|
T59 |
1 |
|
T83 |
1 |
| true |
555 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2568 |
1 |
|
T1 |
1 |
|
T16 |
16 |
|
T18 |
11 |
| others[1] |
2554 |
1 |
|
T16 |
14 |
|
T18 |
17 |
|
T4 |
1 |
| others[2] |
2547 |
1 |
|
T16 |
16 |
|
T18 |
9 |
|
T58 |
21 |
| others[3] |
4246 |
1 |
|
T16 |
16 |
|
T17 |
1 |
|
T18 |
19 |
| false |
1374 |
1 |
|
T16 |
5 |
|
T18 |
6 |
|
T58 |
12 |
| true |
1534 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10449 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T16 |
67 |
| others[1] |
261 |
1 |
|
T34 |
1 |
|
T25 |
1 |
|
T243 |
1 |
| others[2] |
244 |
1 |
|
T20 |
1 |
|
T24 |
1 |
|
T59 |
1 |
| others[3] |
468 |
1 |
|
T94 |
1 |
|
T78 |
2 |
|
T120 |
1 |
| false |
151 |
1 |
|
T17 |
1 |
|
T78 |
1 |
|
T119 |
1 |
| true |
3250 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10645 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T58 |
11 |
| others[1] |
507 |
1 |
|
T24 |
1 |
|
T58 |
7 |
|
T34 |
1 |
| others[2] |
415 |
1 |
|
T4 |
1 |
|
T46 |
1 |
|
T47 |
1 |
| others[3] |
766 |
1 |
|
T33 |
1 |
|
T58 |
13 |
|
T82 |
3 |
| false |
242 |
1 |
|
T58 |
9 |
|
T83 |
1 |
|
T30 |
1 |
| true |
2248 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10419 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T51 |
1 |
| others[1] |
284 |
1 |
|
T46 |
1 |
|
T118 |
1 |
|
T30 |
1 |
| others[2] |
257 |
1 |
|
T133 |
1 |
|
T135 |
1 |
|
T168 |
1 |
| others[3] |
434 |
1 |
|
T132 |
1 |
|
T119 |
1 |
|
T133 |
1 |
| false |
134 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T238 |
1 |
| true |
3295 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10421 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T95 |
202 |
| others[1] |
255 |
1 |
|
T1 |
1 |
|
T34 |
1 |
|
T116 |
1 |
| others[2] |
240 |
1 |
|
T46 |
1 |
|
T51 |
1 |
|
T118 |
1 |
| others[3] |
411 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T59 |
1 |
| false |
129 |
1 |
|
T19 |
1 |
|
T59 |
1 |
|
T64 |
4 |
| true |
3367 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10991 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T33 |
1 |
| others[1] |
830 |
1 |
|
T58 |
15 |
|
T78 |
1 |
|
T82 |
2 |
| others[2] |
732 |
1 |
|
T4 |
1 |
|
T58 |
20 |
|
T78 |
2 |
| others[3] |
1316 |
1 |
|
T58 |
28 |
|
T59 |
1 |
|
T78 |
2 |
| false |
416 |
1 |
|
T17 |
1 |
|
T58 |
2 |
|
T94 |
1 |
| true |
538 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10955 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T58 |
9 |
| others[1] |
803 |
1 |
|
T33 |
1 |
|
T58 |
16 |
|
T34 |
1 |
| others[2] |
805 |
1 |
|
T58 |
17 |
|
T78 |
2 |
|
T82 |
1 |
| others[3] |
1284 |
1 |
|
T58 |
38 |
|
T59 |
1 |
|
T78 |
3 |
| false |
425 |
1 |
|
T58 |
7 |
|
T78 |
1 |
|
T82 |
1 |
| true |
551 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2548 |
1 |
|
T16 |
8 |
|
T17 |
1 |
|
T18 |
10 |
| others[1] |
2594 |
1 |
|
T16 |
15 |
|
T18 |
12 |
|
T19 |
1 |
| others[2] |
2552 |
1 |
|
T1 |
1 |
|
T16 |
12 |
|
T18 |
5 |
| others[3] |
4307 |
1 |
|
T16 |
25 |
|
T18 |
31 |
|
T58 |
23 |
| false |
1286 |
1 |
|
T16 |
7 |
|
T18 |
4 |
|
T58 |
12 |
| true |
1536 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10442 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T46 |
1 |
| others[1] |
266 |
1 |
|
T17 |
1 |
|
T24 |
1 |
|
T43 |
1 |
| others[2] |
287 |
1 |
|
T59 |
1 |
|
T139 |
1 |
|
T135 |
1 |
| others[3] |
407 |
1 |
|
T3 |
1 |
|
T33 |
1 |
|
T94 |
1 |
| false |
133 |
1 |
|
T2 |
1 |
|
T78 |
2 |
|
T43 |
2 |
| true |
3288 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10646 |
1 |
|
T3 |
1 |
|
T16 |
67 |
|
T18 |
62 |
| others[1] |
456 |
1 |
|
T20 |
1 |
|
T58 |
7 |
|
T78 |
1 |
| others[2] |
518 |
1 |
|
T46 |
1 |
|
T24 |
1 |
|
T58 |
8 |
| others[3] |
776 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T58 |
13 |
| false |
225 |
1 |
|
T58 |
2 |
|
T392 |
1 |
|
T82 |
1 |
| true |
2202 |
1 |
|
T17 |
1 |
|
T4 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10405 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T4 |
1 |
| others[1] |
258 |
1 |
|
T46 |
1 |
|
T133 |
1 |
|
T30 |
1 |
| others[2] |
272 |
1 |
|
T168 |
1 |
|
T243 |
1 |
|
T43 |
2 |
| others[3] |
446 |
1 |
|
T20 |
1 |
|
T119 |
1 |
|
T139 |
1 |
| false |
126 |
1 |
|
T237 |
1 |
|
T64 |
6 |
|
T364 |
1 |
| true |
3316 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10409 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T33 |
1 |
| others[1] |
266 |
1 |
|
T19 |
1 |
|
T393 |
1 |
|
T133 |
1 |
| others[2] |
247 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T119 |
1 |
| others[3] |
442 |
1 |
|
T17 |
1 |
|
T132 |
1 |
|
T120 |
1 |
| false |
126 |
1 |
|
T34 |
1 |
|
T64 |
5 |
|
T69 |
7 |
| true |
3333 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10972 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T58 |
26 |
| others[1] |
795 |
1 |
|
T4 |
1 |
|
T58 |
12 |
|
T78 |
2 |
| others[2] |
765 |
1 |
|
T58 |
16 |
|
T34 |
1 |
|
T78 |
3 |
| others[3] |
1287 |
1 |
|
T33 |
1 |
|
T58 |
23 |
|
T78 |
2 |
| false |
466 |
1 |
|
T58 |
10 |
|
T78 |
1 |
|
T82 |
1 |
| true |
538 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10915 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T58 |
15 |
| others[1] |
802 |
1 |
|
T33 |
1 |
|
T58 |
17 |
|
T78 |
3 |
| others[2] |
840 |
1 |
|
T58 |
22 |
|
T78 |
2 |
|
T82 |
1 |
| others[3] |
1290 |
1 |
|
T58 |
26 |
|
T78 |
1 |
|
T82 |
3 |
| false |
422 |
1 |
|
T58 |
7 |
|
T34 |
1 |
|
T59 |
1 |
| true |
554 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2540 |
1 |
|
T1 |
1 |
|
T16 |
19 |
|
T18 |
12 |
| others[1] |
2586 |
1 |
|
T16 |
8 |
|
T18 |
14 |
|
T58 |
18 |
| others[2] |
2588 |
1 |
|
T16 |
10 |
|
T18 |
8 |
|
T58 |
17 |
| others[3] |
4236 |
1 |
|
T16 |
27 |
|
T18 |
22 |
|
T4 |
1 |
| false |
1359 |
1 |
|
T16 |
3 |
|
T18 |
6 |
|
T33 |
1 |
| true |
1514 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10414 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T78 |
1 |
| others[1] |
268 |
1 |
|
T1 |
1 |
|
T20 |
1 |
|
T133 |
1 |
| others[2] |
268 |
1 |
|
T17 |
1 |
|
T4 |
1 |
|
T59 |
1 |
| others[3] |
472 |
1 |
|
T2 |
1 |
|
T34 |
1 |
|
T78 |
6 |
| false |
147 |
1 |
|
T3 |
1 |
|
T78 |
1 |
|
T143 |
1 |
| true |
3254 |
1 |
|
T19 |
1 |
|
T46 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10626 |
1 |
|
T2 |
1 |
|
T16 |
67 |
|
T17 |
1 |
| others[1] |
465 |
1 |
|
T58 |
13 |
|
T52 |
1 |
|
T59 |
1 |
| others[2] |
446 |
1 |
|
T1 |
1 |
|
T33 |
1 |
|
T58 |
5 |
| others[3] |
786 |
1 |
|
T3 |
1 |
|
T24 |
1 |
|
T51 |
1 |
| false |
245 |
1 |
|
T47 |
1 |
|
T58 |
5 |
|
T78 |
1 |
| true |
2255 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10401 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T95 |
202 |
| others[1] |
271 |
1 |
|
T30 |
1 |
|
T63 |
1 |
|
T237 |
1 |
| others[2] |
275 |
1 |
|
T2 |
1 |
|
T19 |
1 |
|
T137 |
1 |
| others[3] |
411 |
1 |
|
T33 |
1 |
|
T51 |
1 |
|
T392 |
1 |
| false |
152 |
1 |
|
T23 |
1 |
|
T64 |
5 |
|
T129 |
1 |
| true |
3313 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10415 |
1 |
|
T1 |
1 |
|
T16 |
67 |
|
T18 |
62 |
| others[1] |
265 |
1 |
|
T64 |
13 |
|
T92 |
1 |
|
T130 |
2 |
| others[2] |
289 |
1 |
|
T59 |
1 |
|
T132 |
1 |
|
T392 |
1 |
| others[3] |
423 |
1 |
|
T33 |
1 |
|
T51 |
1 |
|
T52 |
1 |
| false |
130 |
1 |
|
T139 |
1 |
|
T63 |
2 |
|
T64 |
4 |
| true |
3301 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10941 |
1 |
|
T16 |
67 |
|
T17 |
1 |
|
T18 |
62 |
| others[1] |
779 |
1 |
|
T58 |
17 |
|
T78 |
2 |
|
T82 |
5 |
| others[2] |
802 |
1 |
|
T58 |
21 |
|
T82 |
1 |
|
T83 |
3 |
| others[3] |
1362 |
1 |
|
T33 |
1 |
|
T58 |
31 |
|
T59 |
2 |
| false |
404 |
1 |
|
T3 |
1 |
|
T58 |
6 |
|
T78 |
2 |
| true |
535 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10918 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T58 |
19 |
| others[1] |
820 |
1 |
|
T58 |
18 |
|
T34 |
1 |
|
T59 |
2 |
| others[2] |
782 |
1 |
|
T46 |
1 |
|
T51 |
1 |
|
T58 |
14 |
| others[3] |
1298 |
1 |
|
T33 |
1 |
|
T58 |
27 |
|
T78 |
3 |
| false |
443 |
1 |
|
T58 |
9 |
|
T78 |
1 |
|
T82 |
1 |
| true |
562 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2561 |
1 |
|
T16 |
7 |
|
T18 |
6 |
|
T19 |
1 |
| others[1] |
2537 |
1 |
|
T16 |
14 |
|
T18 |
16 |
|
T58 |
19 |
| others[2] |
2648 |
1 |
|
T16 |
14 |
|
T18 |
16 |
|
T58 |
20 |
| others[3] |
4276 |
1 |
|
T16 |
22 |
|
T17 |
1 |
|
T18 |
17 |
| false |
1274 |
1 |
|
T16 |
10 |
|
T18 |
7 |
|
T58 |
5 |
| true |
1527 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10428 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T34 |
1 |
| others[1] |
259 |
1 |
|
T59 |
1 |
|
T43 |
2 |
|
T64 |
17 |
| others[2] |
298 |
1 |
|
T17 |
1 |
|
T78 |
1 |
|
T79 |
2 |
| others[3] |
457 |
1 |
|
T52 |
1 |
|
T78 |
4 |
|
T393 |
1 |
| false |
120 |
1 |
|
T392 |
1 |
|
T359 |
1 |
|
T43 |
1 |
| true |
3261 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |