Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10630 |
1 |
|
T2 |
1 |
|
T16 |
67 |
|
T18 |
62 |
| others[1] |
490 |
1 |
|
T58 |
10 |
|
T83 |
1 |
|
T68 |
1 |
| others[2] |
475 |
1 |
|
T46 |
1 |
|
T58 |
8 |
|
T82 |
2 |
| others[3] |
747 |
1 |
|
T1 |
1 |
|
T58 |
18 |
|
T59 |
2 |
| false |
280 |
1 |
|
T51 |
1 |
|
T58 |
4 |
|
T34 |
1 |
| true |
2201 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10434 |
1 |
|
T2 |
1 |
|
T16 |
67 |
|
T18 |
62 |
| others[1] |
221 |
1 |
|
T59 |
1 |
|
T120 |
1 |
|
T237 |
1 |
| others[2] |
282 |
1 |
|
T119 |
1 |
|
T143 |
1 |
|
T299 |
1 |
| others[3] |
447 |
1 |
|
T17 |
1 |
|
T132 |
1 |
|
T392 |
1 |
| false |
139 |
1 |
|
T20 |
1 |
|
T135 |
1 |
|
T43 |
1 |
| true |
3300 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10430 |
1 |
|
T2 |
1 |
|
T16 |
67 |
|
T18 |
62 |
| others[1] |
248 |
1 |
|
T52 |
1 |
|
T132 |
1 |
|
T139 |
1 |
| others[2] |
245 |
1 |
|
T33 |
1 |
|
T34 |
1 |
|
T120 |
1 |
| others[3] |
412 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T392 |
1 |
| false |
143 |
1 |
|
T118 |
1 |
|
T133 |
1 |
|
T143 |
1 |
| true |
3345 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10943 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T58 |
6 |
| others[1] |
818 |
1 |
|
T17 |
1 |
|
T4 |
1 |
|
T58 |
22 |
| others[2] |
824 |
1 |
|
T1 |
1 |
|
T58 |
21 |
|
T94 |
1 |
| others[3] |
1297 |
1 |
|
T33 |
1 |
|
T58 |
27 |
|
T59 |
1 |
| false |
406 |
1 |
|
T58 |
11 |
|
T83 |
1 |
|
T143 |
1 |
| true |
535 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10998 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T58 |
19 |
| others[1] |
796 |
1 |
|
T58 |
13 |
|
T34 |
1 |
|
T59 |
1 |
| others[2] |
753 |
1 |
|
T33 |
1 |
|
T58 |
24 |
|
T82 |
4 |
| others[3] |
1330 |
1 |
|
T58 |
19 |
|
T78 |
4 |
|
T82 |
4 |
| false |
403 |
1 |
|
T58 |
12 |
|
T167 |
1 |
|
T64 |
12 |
| true |
543 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2593 |
1 |
|
T2 |
1 |
|
T16 |
14 |
|
T18 |
9 |
| others[1] |
2642 |
1 |
|
T16 |
15 |
|
T18 |
8 |
|
T19 |
1 |
| others[2] |
2498 |
1 |
|
T16 |
15 |
|
T18 |
15 |
|
T4 |
1 |
| others[3] |
4244 |
1 |
|
T16 |
18 |
|
T18 |
23 |
|
T51 |
1 |
| false |
1307 |
1 |
|
T16 |
5 |
|
T18 |
7 |
|
T33 |
1 |
| true |
1539 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10449 |
1 |
|
T1 |
1 |
|
T16 |
67 |
|
T18 |
62 |
| others[1] |
270 |
1 |
|
T17 |
1 |
|
T120 |
1 |
|
T118 |
1 |
| others[2] |
269 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T51 |
1 |
| others[3] |
444 |
1 |
|
T19 |
1 |
|
T34 |
1 |
|
T52 |
1 |
| false |
142 |
1 |
|
T78 |
1 |
|
T135 |
1 |
|
T64 |
3 |
| true |
3249 |
1 |
|
T20 |
1 |
|
T46 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10609 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T4 |
1 |
| others[1] |
459 |
1 |
|
T33 |
1 |
|
T58 |
7 |
|
T5 |
1 |
| others[2] |
473 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T46 |
1 |
| others[3] |
761 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T24 |
1 |
| false |
240 |
1 |
|
T58 |
7 |
|
T9 |
1 |
|
T30 |
1 |
| true |
2281 |
1 |
|
T19 |
1 |
|
T20 |
1 |
|
T51 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10406 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T24 |
1 |
| others[1] |
267 |
1 |
|
T19 |
1 |
|
T393 |
1 |
|
T63 |
1 |
| others[2] |
256 |
1 |
|
T4 |
1 |
|
T94 |
1 |
|
T132 |
1 |
| others[3] |
432 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T46 |
1 |
| false |
133 |
1 |
|
T133 |
1 |
|
T139 |
1 |
|
T43 |
1 |
| true |
3329 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10389 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T95 |
202 |
| others[1] |
247 |
1 |
|
T34 |
1 |
|
T116 |
1 |
|
T64 |
16 |
| others[2] |
260 |
1 |
|
T19 |
1 |
|
T132 |
1 |
|
T248 |
1 |
| others[3] |
441 |
1 |
|
T17 |
1 |
|
T59 |
2 |
|
T392 |
1 |
| false |
125 |
1 |
|
T64 |
3 |
|
T91 |
1 |
|
T69 |
1 |
| true |
3361 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10985 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T51 |
1 |
| others[1] |
811 |
1 |
|
T46 |
1 |
|
T58 |
17 |
|
T52 |
1 |
| others[2] |
767 |
1 |
|
T58 |
23 |
|
T78 |
2 |
|
T83 |
1 |
| others[3] |
1312 |
1 |
|
T33 |
1 |
|
T58 |
25 |
|
T34 |
1 |
| false |
399 |
1 |
|
T58 |
4 |
|
T59 |
1 |
|
T82 |
3 |
| true |
549 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10947 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T58 |
11 |
| others[1] |
828 |
1 |
|
T58 |
19 |
|
T78 |
1 |
|
T82 |
2 |
| others[2] |
775 |
1 |
|
T33 |
1 |
|
T58 |
22 |
|
T78 |
3 |
| others[3] |
1293 |
1 |
|
T58 |
30 |
|
T34 |
1 |
|
T59 |
1 |
| false |
422 |
1 |
|
T58 |
5 |
|
T82 |
1 |
|
T83 |
2 |
| true |
558 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2619 |
1 |
|
T16 |
11 |
|
T18 |
14 |
|
T58 |
14 |
| others[1] |
2564 |
1 |
|
T16 |
17 |
|
T18 |
13 |
|
T33 |
1 |
| others[2] |
2506 |
1 |
|
T16 |
15 |
|
T18 |
11 |
|
T58 |
21 |
| others[3] |
4299 |
1 |
|
T16 |
18 |
|
T17 |
1 |
|
T18 |
20 |
| false |
1312 |
1 |
|
T16 |
6 |
|
T18 |
4 |
|
T58 |
8 |
| true |
1523 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10411 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T52 |
1 |
| others[1] |
268 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T4 |
1 |
| others[2] |
263 |
1 |
|
T78 |
1 |
|
T63 |
1 |
|
T227 |
1 |
| others[3] |
446 |
1 |
|
T33 |
1 |
|
T78 |
1 |
|
T393 |
1 |
| false |
132 |
1 |
|
T34 |
1 |
|
T78 |
1 |
|
T132 |
1 |
| true |
3303 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T19 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10645 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T58 |
7 |
| others[1] |
473 |
1 |
|
T17 |
1 |
|
T33 |
1 |
|
T51 |
1 |
| others[2] |
433 |
1 |
|
T20 |
1 |
|
T24 |
1 |
|
T58 |
12 |
| others[3] |
776 |
1 |
|
T2 |
1 |
|
T47 |
1 |
|
T58 |
17 |
| false |
241 |
1 |
|
T58 |
4 |
|
T9 |
1 |
|
T82 |
1 |
| true |
2255 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10413 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T95 |
202 |
| others[1] |
251 |
1 |
|
T17 |
1 |
|
T34 |
1 |
|
T248 |
1 |
| others[2] |
291 |
1 |
|
T59 |
1 |
|
T392 |
1 |
|
T30 |
1 |
| others[3] |
428 |
1 |
|
T1 |
1 |
|
T24 |
1 |
|
T51 |
1 |
| false |
134 |
1 |
|
T19 |
1 |
|
T59 |
1 |
|
T43 |
2 |
| true |
3306 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10427 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T4 |
1 |
| others[1] |
253 |
1 |
|
T19 |
1 |
|
T52 |
1 |
|
T132 |
1 |
| others[2] |
247 |
1 |
|
T1 |
1 |
|
T33 |
1 |
|
T64 |
15 |
| others[3] |
441 |
1 |
|
T51 |
1 |
|
T34 |
1 |
|
T59 |
1 |
| false |
117 |
1 |
|
T2 |
1 |
|
T239 |
1 |
|
T64 |
11 |
| true |
3338 |
1 |
|
T3 |
1 |
|
T17 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10959 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T58 |
16 |
| others[1] |
811 |
1 |
|
T19 |
1 |
|
T33 |
1 |
|
T58 |
15 |
| others[2] |
806 |
1 |
|
T58 |
16 |
|
T78 |
1 |
|
T82 |
2 |
| others[3] |
1307 |
1 |
|
T58 |
28 |
|
T5 |
1 |
|
T59 |
1 |
| false |
392 |
1 |
|
T58 |
12 |
|
T34 |
1 |
|
T83 |
1 |
| true |
548 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10975 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T33 |
1 |
| others[1] |
767 |
1 |
|
T1 |
1 |
|
T58 |
11 |
|
T34 |
1 |
| others[2] |
815 |
1 |
|
T58 |
18 |
|
T78 |
4 |
|
T82 |
2 |
| others[3] |
1285 |
1 |
|
T3 |
1 |
|
T58 |
33 |
|
T78 |
2 |
| false |
422 |
1 |
|
T58 |
6 |
|
T78 |
1 |
|
T83 |
2 |
| true |
559 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2569 |
1 |
|
T16 |
11 |
|
T18 |
9 |
|
T33 |
1 |
| others[1] |
2485 |
1 |
|
T1 |
1 |
|
T16 |
14 |
|
T18 |
15 |
| others[2] |
2608 |
1 |
|
T16 |
20 |
|
T18 |
10 |
|
T19 |
1 |
| others[3] |
4278 |
1 |
|
T16 |
19 |
|
T18 |
18 |
|
T4 |
1 |
| false |
1332 |
1 |
|
T16 |
3 |
|
T18 |
10 |
|
T58 |
12 |
| true |
1551 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10428 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T95 |
202 |
| others[1] |
239 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T34 |
1 |
| others[2] |
301 |
1 |
|
T46 |
1 |
|
T24 |
1 |
|
T52 |
1 |
| others[3] |
441 |
1 |
|
T19 |
1 |
|
T94 |
1 |
|
T392 |
1 |
| false |
144 |
1 |
|
T79 |
1 |
|
T64 |
7 |
|
T44 |
1 |
| true |
3270 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10625 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T19 |
1 |
| others[1] |
481 |
1 |
|
T17 |
1 |
|
T20 |
1 |
|
T24 |
1 |
| others[2] |
456 |
1 |
|
T46 |
1 |
|
T58 |
6 |
|
T119 |
1 |
| others[3] |
793 |
1 |
|
T1 |
1 |
|
T58 |
17 |
|
T34 |
1 |
| false |
236 |
1 |
|
T4 |
1 |
|
T33 |
1 |
|
T58 |
5 |
| true |
2232 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T51 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10414 |
1 |
|
T1 |
1 |
|
T16 |
67 |
|
T18 |
62 |
| others[1] |
269 |
1 |
|
T4 |
1 |
|
T19 |
1 |
|
T46 |
1 |
| others[2] |
242 |
1 |
|
T34 |
1 |
|
T52 |
1 |
|
T53 |
1 |
| others[3] |
417 |
1 |
|
T59 |
1 |
|
T143 |
1 |
|
T63 |
1 |
| false |
125 |
1 |
|
T51 |
1 |
|
T132 |
1 |
|
T93 |
1 |
| true |
3356 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10424 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T95 |
202 |
| others[1] |
239 |
1 |
|
T52 |
1 |
|
T393 |
1 |
|
T63 |
1 |
| others[2] |
270 |
1 |
|
T46 |
1 |
|
T392 |
1 |
|
T119 |
1 |
| others[3] |
414 |
1 |
|
T33 |
1 |
|
T59 |
1 |
|
T143 |
1 |
| false |
150 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T143 |
1 |
| true |
3326 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10915 |
1 |
|
T16 |
67 |
|
T18 |
62 |
|
T58 |
20 |
| others[1] |
773 |
1 |
|
T58 |
14 |
|
T78 |
1 |
|
T82 |
2 |
| others[2] |
802 |
1 |
|
T58 |
16 |
|
T34 |
1 |
|
T78 |
2 |
| others[3] |
1383 |
1 |
|
T3 |
1 |
|
T33 |
1 |
|
T58 |
32 |
| false |
413 |
1 |
|
T58 |
5 |
|
T82 |
3 |
|
T167 |
1 |
| true |
537 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T17 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |