Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	250184	1		T1	576		T2	1433		T3	7
auto[FlashEraseBank]	277839	1		T1	525		T2	1959		T3	3

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	271477	1		T1	1101		T2	1374		T3	9
auto[FlashOpProgram]	236021	1		T2	2018		T3	1		T15	160
auto[FlashOpErase]	16525	1		T15	12		T16	97		T18	41
auto[FlashOpInvalid]	4000	1		T80	200		T134	200		T318	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	271477	1		T1	1101		T2	1374		T3	9
op[FlashOpProgram]	236021	1		T2	2018		T3	1		T15	160
op[FlashOpErase]	16525	1		T15	12		T16	97		T18	41
read_erase_read	547	1		T15	3		T24	14		T29	1
read_prog_read	816	1		T2	7		T3	1		T4	9

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	384388	1		T1	898		T2	2765		T3	1
auto[FlashPartInfo]	140291	1		T1	193		T2	610		T3	8
auto[FlashPartInfo1]	842	1		T1	4		T2	2		T4	3
auto[FlashPartInfo2]	2502	1		T1	6		T2	15		T3	1

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	199352	1		T1	898		T2	975		T3	1
auto[FlashPartData]	auto[FlashOpProgram]	177554	1		T2	1790		T18	61		T4	1967
auto[FlashPartData]	auto[FlashOpErase]	3588	1		T18	41		T24	7		T68	1
auto[FlashPartData]	auto[FlashOpInvalid]	3894	1		T80	198		T134	196		T318	198
auto[FlashPartInfo]	auto[FlashOpRead]	69902	1		T1	193		T2	386		T3	7
auto[FlashPartInfo]	auto[FlashOpProgram]	57396	1		T2	224		T3	1		T15	160
auto[FlashPartInfo]	auto[FlashOpErase]	12909	1		T15	12		T16	97		T24	11
auto[FlashPartInfo]	auto[FlashOpInvalid]	84	1		T80	2		T134	4		T318	2
auto[FlashPartInfo1]	auto[FlashOpRead]	666	1		T1	4		T2	2		T4	3
auto[FlashPartInfo1]	auto[FlashOpProgram]	166	1		T35	32		T64	1		T122	1
auto[FlashPartInfo1]	auto[FlashOpErase]	4	1		T122	1		T145	1		T124	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	6	1		T122	2		T124	2		T420	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1557	1		T1	6		T2	11		T3	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	905	1		T2	4		T4	4		T51	9
auto[FlashPartInfo2]	auto[FlashOpErase]	24	1		T63	1		T131	1		T421	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	16	1		T160	6		T422	2		T423	2