Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32672	1		T15	4		T16	180		T18	1
auto[1]	36	1		T23	1		T237	1		T299	12
auto[2]	55	1		T237	14		T300	1		T207	12
auto[3]	258	1		T3	1		T24	11		T135	12

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	8258	1		T15	1		T16	45		T24	2
evic_idx[1]	8262	1		T3	1		T15	1		T16	45
evic_idx[2]	8254	1		T15	1		T16	45		T18	1
evic_idx[3]	8247	1		T15	1		T16	45		T24	3

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	32094	1		T15	4		T16	180		T18	1
evic_op[2]	301	1		T3	1		T78	16		T79	4

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7956	1		T15	1		T16	45		T95	142
evic_idx[0]	evic_op[1]	auto[1]	7	1		T237	1		T299	4		T424	2
evic_idx[0]	evic_op[1]	auto[2]	7	1		T237	4		T425	1		T426	2
evic_idx[0]	evic_op[1]	auto[3]	56	1		T24	2		T135	3		T427	3
evic_idx[0]	evic_op[2]	auto[0]	59	1		T78	4		T79	1		T413	1
evic_idx[0]	evic_op[2]	auto[1]	4	1		T23	1		T204	1		T428	1
evic_idx[0]	evic_op[2]	auto[2]	1	1		T236	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[3]	11	1		T93	1		T225	1		T429	1
evic_idx[1]	evic_op[1]	auto[0]	7959	1		T15	1		T16	45		T95	142
evic_idx[1]	evic_op[1]	auto[1]	7	1		T299	4		T430	1		T424	2
evic_idx[1]	evic_op[1]	auto[2]	7	1		T237	4		T425	1		T426	2
evic_idx[1]	evic_op[1]	auto[3]	54	1		T24	3		T135	2		T299	2
evic_idx[1]	evic_op[2]	auto[0]	58	1		T78	4		T79	1		T413	1
evic_idx[1]	evic_op[2]	auto[1]	4	1		T300	1		T431	1		T432	1
evic_idx[1]	evic_op[2]	auto[2]	2	1		T300	1		T428	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	14	1		T3	1		T227	1		T202	1
evic_idx[2]	evic_op[1]	auto[0]	7955	1		T15	1		T16	45		T18	1
evic_idx[2]	evic_op[1]	auto[1]	4	1		T299	1		T430	1		T424	2
evic_idx[2]	evic_op[1]	auto[2]	7	1		T237	3		T425	1		T426	2
evic_idx[2]	evic_op[1]	auto[3]	56	1		T24	3		T135	5		T237	2
evic_idx[2]	evic_op[2]	auto[0]	62	1		T78	4		T79	1		T413	1
evic_idx[2]	evic_op[2]	auto[1]	4	1		T155	1		T433	1		T434	1
evic_idx[2]	evic_op[2]	auto[2]	2	1		T435	1		T428	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	8	1		T203	1		T205	1		T230	1
evic_idx[3]	evic_op[1]	auto[0]	7955	1		T15	1		T16	45		T95	142
evic_idx[3]	evic_op[1]	auto[1]	5	1		T299	3		T424	2		-	-
evic_idx[3]	evic_op[1]	auto[2]	5	1		T237	3		T425	1		T426	1
evic_idx[3]	evic_op[1]	auto[3]	54	1		T24	3		T135	2		T237	2
evic_idx[3]	evic_op[2]	auto[0]	62	1		T78	4		T79	1		T413	1
evic_idx[3]	evic_op[2]	auto[1]	1	1		T436	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[2]	4	1		T236	1		T437	1		T435	2
evic_idx[3]	evic_op[2]	auto[3]	5	1		T438	1		T439	1		T440	1