Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	51243	1		T355	15775		T356	1546		T357	16100
rd_lvl[2]	77598	1		T168	12228		T355	11537		T358	1899
rd_lvl[3]	18765	1		T168	338		T359	1054		T360	1317
rd_lvl[4]	39947	1		T359	1121		T360	5344		T361	2291
rd_lvl[5]	17666	1		T20	2183		T359	57		T301	2392
rd_lvl[6]	11568	1		T20	1173		T359	74		T301	1166
rd_lvl[7]	13286	1		T53	1603		T361	425		T362	743
rd_lvl[8]	17575	1		T53	1293		T363	3125		T361	1171
rd_lvl[9]	6495	1		T34	222		T363	353		T364	592
rd_lvl[10]	9096	1		T34	1324		T359	1		T32	218
rd_lvl[11]	5440	1		T31	67		T32	211		T152	630
rd_lvl[12]	7777	1		T31	9		T32	1		T152	1002
rd_lvl[13]	4604	1		T33	661		T30	249		T359	75
rd_lvl[14]	9961	1		T33	1003		T30	90		T31	3
rd_lvl[15]	1042	1		T365	156		T366	369		T367	43