Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	435245	1		T1	2		T2	2		T3	1
all_pins[1]	435245	1		T1	2		T2	2		T3	1
all_pins[2]	435245	1		T1	2		T2	2		T3	1
all_pins[3]	435245	1		T1	2		T2	2		T3	1
all_pins[4]	435245	1		T1	2		T2	2		T3	1
all_pins[5]	435245	1		T1	2		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2191847	1		T1	12		T2	12		T3	6
values[0x1]	419623	1		T20	5007		T33	3328		T34	3092
transitions[0x0=>0x1]	383356	1		T20	4902		T33	3328		T34	3092
transitions[0x1=>0x0]	383343	1		T20	4902		T33	3328		T34	3092

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	435087	1		T1	2		T2	2		T3	1
all_pins[0]	values[0x1]	158	1		T281	4		T282	3		T283	3
all_pins[0]	transitions[0x0=>0x1]	73	1		T281	3		T282	2		T369	1
all_pins[0]	transitions[0x1=>0x0]	77	1		T281	1		T283	2		T352	4
all_pins[1]	values[0x0]	435083	1		T1	2		T2	2		T3	1
all_pins[1]	values[0x1]	162	1		T281	2		T282	1		T283	5
all_pins[1]	transitions[0x0=>0x1]	138	1		T281	2		T282	1		T283	3
all_pins[1]	transitions[0x1=>0x0]	333	1		T365	72		T370	1		T367	23
all_pins[2]	values[0x0]	434888	1		T1	2		T2	2		T3	1
all_pins[2]	values[0x1]	357	1		T365	72		T370	1		T367	23
all_pins[2]	transitions[0x0=>0x1]	40	1		T282	1		T350	1		T371	1
all_pins[2]	transitions[0x1=>0x0]	292333	1		T20	3356		T33	1664		T34	1546
all_pins[3]	values[0x0]	142595	1		T1	2		T2	2		T3	1
all_pins[3]	values[0x1]	292650	1		T20	3356		T33	1664		T34	1546
all_pins[3]	transitions[0x0=>0x1]	256866	1		T20	3251		T33	1664		T34	1546
all_pins[3]	transitions[0x1=>0x0]	90451	1		T20	1546		T33	1664		T34	1546
all_pins[4]	values[0x0]	309010	1		T1	2		T2	2		T3	1
all_pins[4]	values[0x1]	126235	1		T20	1651		T33	1664		T34	1546
all_pins[4]	transitions[0x0=>0x1]	126214	1		T20	1651		T33	1664		T34	1546
all_pins[4]	transitions[0x1=>0x0]	40	1		T282	2		T283	3		T351	2
all_pins[5]	values[0x0]	435184	1		T1	2		T2	2		T3	1
all_pins[5]	values[0x1]	61	1		T282	2		T283	3		T351	2
all_pins[5]	transitions[0x0=>0x1]	25	1		T283	2		T372	1		T373	1
all_pins[5]	transitions[0x1=>0x0]	109	1		T281	4		T282	2		T283	1