Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1		T281	7		T282	7		T283	4
all_values[1]	278	1		T281	7		T282	7		T283	4
all_values[2]	278	1		T281	7		T282	7		T283	4
all_values[3]	278	1		T281	7		T282	7		T283	4
all_values[4]	278	1		T281	7		T282	7		T283	4
all_values[5]	278	1		T281	7		T282	7		T283	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	922	1		T281	25		T282	28		T283	12
auto[1]	746	1		T281	17		T282	14		T283	12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	545	1		T281	13		T282	11		T283	5
auto[1]	1123	1		T281	29		T282	31		T283	19

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	986	1		T281	26		T282	21		T283	11
auto[1]	682	1		T281	16		T282	21		T283	13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	91	1		T281	3		T282	2		T283	1
all_values[0]	auto[0]	auto[1]	auto[1]	69	1		T283	1		T350	1		T351	2
all_values[0]	auto[1]	auto[0]	auto[1]	60	1		T282	3		T283	1		T352	2
all_values[0]	auto[1]	auto[1]	auto[1]	58	1		T281	4		T282	2		T283	1
all_values[1]	auto[0]	auto[0]	auto[1]	83	1		T281	5		T282	4		T353	1
all_values[1]	auto[0]	auto[1]	auto[1]	89	1		T281	2		T282	1		T283	2
all_values[1]	auto[1]	auto[0]	auto[1]	60	1		T282	2		T283	1		T352	1
all_values[1]	auto[1]	auto[1]	auto[1]	46	1		T283	1		T352	2		T350	1
all_values[2]	auto[0]	auto[0]	auto[0]	104	1		T281	2		T282	3		T283	1
all_values[2]	auto[0]	auto[1]	auto[0]	65	1		T281	1		T283	1		T352	2
all_values[2]	auto[1]	auto[0]	auto[1]	54	1		T281	4		T282	2		T283	1
all_values[2]	auto[1]	auto[1]	auto[1]	55	1		T282	2		T283	1		T350	1
all_values[3]	auto[0]	auto[0]	auto[0]	86	1		T281	2		T282	2		T283	1
all_values[3]	auto[0]	auto[1]	auto[0]	76	1		T281	2		T282	2		T283	1
all_values[3]	auto[1]	auto[0]	auto[1]	60	1		T282	2		T283	1		T352	2
all_values[3]	auto[1]	auto[1]	auto[1]	56	1		T281	3		T282	1		T283	1
all_values[4]	auto[0]	auto[0]	auto[0]	64	1		T281	2		T282	3		T352	2
all_values[4]	auto[0]	auto[0]	auto[1]	25	1		T281	2		T283	1		T351	2
all_values[4]	auto[0]	auto[1]	auto[0]	47	1		T282	1		T350	1		T353	1
all_values[4]	auto[0]	auto[1]	auto[1]	27	1		T282	1		T350	1		T353	1
all_values[4]	auto[1]	auto[0]	auto[1]	58	1		T281	1		T283	3		T352	2
all_values[4]	auto[1]	auto[1]	auto[1]	57	1		T281	2		T282	2		T350	2
all_values[5]	auto[0]	auto[0]	auto[0]	70	1		T281	1		T283	1		T352	1
all_values[5]	auto[0]	auto[0]	auto[1]	31	1		T281	1		T282	2		T352	1
all_values[5]	auto[0]	auto[1]	auto[0]	33	1		T281	3		T353	2		T351	1
all_values[5]	auto[0]	auto[1]	auto[1]	26	1		T283	1		T351	1		T354	1
all_values[5]	auto[1]	auto[0]	auto[1]	76	1		T281	2		T282	3		T352	2
all_values[5]	auto[1]	auto[1]	auto[1]	42	1		T282	2		T283	2		T353	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal