Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	347123	1		T1	2		T2	1		T3	2
all_values[1]	347123	1		T1	2		T2	1		T3	2
all_values[2]	347123	1		T1	2		T2	1		T3	2
all_values[3]	347123	1		T1	2		T2	1		T3	2
all_values[4]	347123	1		T1	2		T2	1		T3	2
all_values[5]	347123	1		T1	2		T2	1		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	700357	1		T1	12		T2	6		T3	12
auto[1]	1382381	1		T5	13152		T6	12976		T26	6660

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1019505	1		T1	7		T2	4		T3	7
auto[1]	1063233	1		T1	5		T2	2		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	346948	1		T1	2		T2	1		T3	2
all_values[0]	auto[1]	auto[1]	175	1		T255	1		T256	6		T257	2
all_values[1]	auto[0]	auto[1]	346960	1		T1	2		T2	1		T3	2
all_values[1]	auto[1]	auto[1]	163	1		T255	4		T256	2		T257	3
all_values[2]	auto[0]	auto[0]	1550	1		T1	2		T2	1		T3	2
all_values[2]	auto[0]	auto[1]	61	1		T255	1		T256	4		T257	2
all_values[2]	auto[1]	auto[0]	345458	1		T5	3288		T6	3244		T26	1665
all_values[2]	auto[1]	auto[1]	54	1		T255	2		T326	5		T328	3
all_values[3]	auto[0]	auto[0]	1548	1		T1	2		T2	1		T3	2
all_values[3]	auto[0]	auto[1]	62	1		T255	1		T257	1		T325	3
all_values[3]	auto[1]	auto[0]	86308	1		T5	1644		T6	1622		T26	1665
all_values[3]	auto[1]	auto[1]	259205	1		T5	1644		T6	1622		T40	5655
all_values[4]	auto[0]	auto[0]	1096	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	496	1		T1	1		T3	1		T19	1
all_values[4]	auto[1]	auto[0]	236603	1		T5	1644		T6	1622		T26	1
all_values[4]	auto[1]	auto[1]	108928	1		T5	1644		T6	1622		T26	1664
all_values[5]	auto[0]	auto[0]	1516	1		T1	2		T2	1		T3	2
all_values[5]	auto[0]	auto[1]	120	1		T41	1		T42	1		T43	1
all_values[5]	auto[1]	auto[0]	345426	1		T5	3288		T6	3244		T26	1665
all_values[5]	auto[1]	auto[1]	61	1		T255	3		T256	1		T325	1