Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	239079	1		T1	100		T2	229		T3	37
auto[FlashEraseBank]	266816	1		T1	1104		T3	47		T5	899

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	258263	1		T1	639		T2	123		T5	1644
auto[FlashOpProgram]	227488	1		T1	515		T2	53		T3	84
auto[FlashOpErase]	16144	1		T1	50		T2	53		T19	5
auto[FlashOpInvalid]	4000	1		T83	200		T84	200		T142	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	258263	1		T1	639		T2	123		T5	1644
op[FlashOpProgram]	227488	1		T1	515		T2	53		T3	84
op[FlashOpErase]	16144	1		T1	50		T2	53		T19	5
read_erase_read	572	1		T1	3		T19	2		T21	10
read_prog_read	887	1		T1	3		T19	3		T46	1

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	366031	1		T1	92		T3	84		T5	1644
auto[FlashPartInfo]	136488	1		T1	1110		T2	229		T19	8
auto[FlashPartInfo1]	857	1		T19	8		T22	2		T47	7
auto[FlashPartInfo2]	2519	1		T1	2		T19	3		T41	10

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	187644	1		T1	31		T5	1644		T6	1622
auto[FlashPartData]	auto[FlashOpProgram]	170827	1		T1	28		T3	84		T19	7
auto[FlashPartData]	auto[FlashOpErase]	3642	1		T1	33		T19	5		T21	14
auto[FlashPartData]	auto[FlashOpInvalid]	3918	1		T83	200		T84	188		T142	196
auto[FlashPartInfo]	auto[FlashOpRead]	68278	1		T1	608		T2	123		T19	3
auto[FlashPartInfo]	auto[FlashOpProgram]	55671	1		T1	485		T2	53		T19	5
auto[FlashPartInfo]	auto[FlashOpErase]	12471	1		T1	17		T2	53		T21	4
auto[FlashPartInfo]	auto[FlashOpInvalid]	68	1		T84	12		T142	2		T387	2
auto[FlashPartInfo1]	auto[FlashOpRead]	688	1		T19	8		T22	2		T47	7
auto[FlashPartInfo1]	auto[FlashOpProgram]	162	1		T116	1		T136	32		T129	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T116	1		T388	1		T389	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T116	2		T388	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1653	1		T19	1		T41	8		T22	3
auto[FlashPartInfo2]	auto[FlashOpProgram]	828	1		T1	2		T19	2		T41	2
auto[FlashPartInfo2]	auto[FlashOpErase]	28	1		T142	1		T134	1		T227	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	10	1		T142	2		T390	2		T391	2